- Preload V into shared memory alongside K to eliminate per-element KV address lookups in the inner softmax/accum loop (doubles smem) - Cache split-KV partial tensors (o_part, ml_part) with static tensors instead of per-call allocation in both decode and paged-decode paths - Force is_causal=True in CUDA decode backend (decode is always causal)
52 lines
1.8 KiB
Plaintext
52 lines
1.8 KiB
Plaintext
#include "attn_dispatchers.cuh"
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#include "attn_entry_utils.cuh"
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torch::Tensor attn_decode(
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torch::Tensor q,
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torch::Tensor k,
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torch::Tensor v,
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c10::optional<torch::Tensor> mask,
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int64_t causal_offset,
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double scale,
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int64_t layout
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) {
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const at::cuda::OptionalCUDAGuard device_guard(device_of(q));
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auto stream = at::cuda::getCurrentCUDAStream();
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AttentionParams<bf16> p;
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attn_pack_params(q, k, v, mask, causal_offset, scale, layout, p);
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TORCH_CHECK(p.q_len == 1, "Q seq_len must be 1");
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TORCH_CHECK(p.head_dim % 32 == 0, "head_dim must be multiple of 32");
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auto O = torch::empty_strided(q.sizes(), q.strides(), q.options());
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auto O_view = (layout == BLHD) ? O.transpose(1, 2) : O;
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p.o = (bf16*)O_view.data_ptr();
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{
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static torch::Tensor s_o_part, s_ml_part;
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int64_t o_needed = (int64_t)p.batch * p.q_head * MAX_SPLITS * p.head_dim;
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auto fopt = torch::TensorOptions().dtype(torch::kFloat32).device(torch::kCUDA);
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if (!s_o_part.defined() || s_o_part.numel() < o_needed) {
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s_o_part = torch::empty({p.batch, p.q_head, MAX_SPLITS, p.head_dim}, fopt);
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s_ml_part = torch::empty({p.batch, p.q_head, MAX_SPLITS, 2}, fopt);
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}
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p.o_part = (float*)s_o_part.data_ptr();
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p.ml_part = (float*)s_ml_part.data_ptr();
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}
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DISPATCH_HEAD_DIM(p.head_dim, dispatch_decode, p, stream);
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C10_CUDA_CHECK(cudaGetLastError());
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return O;
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}
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PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
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m.def("attn_decode", &attn_decode,
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py::arg("q"),
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py::arg("k"),
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py::arg("v"),
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py::arg("mask") = py::none(),
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py::arg("causal_offset") = -1,
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py::arg("scale") = 0.0,
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py::arg("layout") = (int64_t)BHLD,
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"GQA decode (tensor-core head-packing on sm_80+, scalar fallback)");
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}
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