ViperEkura
bf239d194c
- merge the quantize launchers into one Tiled template; extract shared cvt_fp8/publish_amax helpers and replace the dtype x format ladder with two-level template dispatch - fold the gemm interior/generic operand loads into one kInterior template and the fast/generic async loads into load_async<kFast>; Policy carries the smem budget - compress kernel comments to the load-bearing invariants, dropping measured-number essays; Policy signature and kernel code unchanged Benchmark: NVIDIA L20, 1.2B model train step fwd+bwd+CE - M=8192: fp8 532.2 -> 530.4 ms (1.26x, noise); tests/extension 65 passed, quantize layouts byte-exact, NT routing diff 0.0
251 lines
10 KiB
Plaintext
251 lines
10 KiB
Plaintext
// CUDA bindings for the two stateless FP8 primitives.
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#include <ATen/cuda/CUDAContext.h>
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#include <c10/cuda/CUDAGuard.h>
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#include <torch/extension.h>
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#include <cstdint>
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#include <mutex>
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#include <unordered_map>
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#include "../common/device.cuh"
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#include "gemm.cuh"
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#include "quantize.cuh"
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using namespace astrai::fp8;
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namespace {
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void check_fp8_device(const torch::Tensor& tensor) {
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static std::mutex mutex;
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static std::unordered_map<int, bool> supported;
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const int device = tensor.device().index();
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{
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std::lock_guard<std::mutex> lock(mutex);
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auto it = supported.find(device);
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if (it != supported.end()) {
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TORCH_CHECK(it->second, "FP8 MMA requires compute capability 8.9+");
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return;
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}
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}
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const auto* properties = at::cuda::getDeviceProperties(device);
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const bool ok = astrai::sm_at_least(
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properties->major, properties->minor, astrai::kMinSmForFp8Major,
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astrai::kMinSmForFp8Minor);
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{
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std::lock_guard<std::mutex> lock(mutex);
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supported.emplace(device, ok);
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}
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TORCH_CHECK(ok, "FP8 MMA requires compute capability 8.9+");
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}
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void check_scale(const torch::Tensor& scale, const torch::Tensor& input) {
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TORCH_CHECK(scale.is_cuda() && scale.device() == input.device() &&
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scale.scalar_type() == torch::kFloat32 && scale.numel() == 1,
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"scale must be a CUDA float32 scalar on the input device");
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}
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// Inner-layout resolution for one GEMM operand. The user flag names the
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// math (0 = last two dims are [rows][contract], 1 = transposed); the
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// storage may independently be a col-major view (.t() of a contiguous
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// buffer), which folds into the returned dispatch flag at zero copy — the
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// kernel's LayoutA/LayoutB tags cover both storages. m/n/k derive from the
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// user flag only. Tensors whose inner dims are neither natural layout fall
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// back to .contiguous().
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bool resolve_operand(const torch::Tensor& t_in, bool flag, int64_t& ld,
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int64_t& batch_stride, torch::Tensor& storage) {
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torch::Tensor t = t_in;
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bool col_major = false;
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if (t.stride(-1) != 1) {
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if (t.stride(-2) == 1) {
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col_major = true;
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} else {
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t = t.contiguous();
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}
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}
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storage = t;
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ld = col_major ? t.stride(-1) : t.stride(-2);
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batch_stride = t.dim() == 3 ? t.stride(0) : 0;
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return flag ^ col_major;
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}
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// Dtype dispatch over the unified quantize launcher.
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template <bool Tiled, FP8Format Fmt>
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void launch_for_dtype(const torch::Tensor& x, const FP8QuantizeParams& p,
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cudaStream_t stream) {
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switch (x.scalar_type()) {
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case torch::kHalf:
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launch_fp8_quantize<Fmt, __half, Tiled>(p, stream);
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break;
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case torch::kFloat32:
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launch_fp8_quantize<Fmt, float, Tiled>(p, stream);
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break;
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default:
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launch_fp8_quantize<Fmt, __nv_bfloat16, Tiled>(p, stream);
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}
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}
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template <bool Tiled>
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void launch_quantize_for(const torch::Tensor& x, const FP8QuantizeParams& p,
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bool e5m2, cudaStream_t stream) {
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if (e5m2)
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launch_for_dtype<Tiled, FP8Format::E5M2>(x, p, stream);
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else
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launch_for_dtype<Tiled, FP8Format::E4M3>(x, p, stream);
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}
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} // namespace
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// Output-layout dispatch: 0 = [rows][cols] row-major (2-tuple return),
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// 1 = transposed [cols][rows] only (2-tuple), 2 = both orientations from a
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// single read (3-tuple). Layouts 1/2 feed the NT GEMM fast path.
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py::object quantize(torch::Tensor x, torch::Tensor scale, int64_t fmt,
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int64_t layout) {
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TORCH_CHECK(x.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(x.scalar_type() == torch::kBFloat16 ||
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x.scalar_type() == torch::kHalf ||
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x.scalar_type() == torch::kFloat32,
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"x must be bf16, fp16 or fp32");
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TORCH_CHECK(fmt == static_cast<int64_t>(FP8Format::E4M3) ||
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fmt == static_cast<int64_t>(FP8Format::E5M2),
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"unsupported quantization type: expected E4M3 (0) or E5M2 (1)");
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TORCH_CHECK(layout >= 0 && layout <= 2,
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"layout must be 0 (row-major), 1 (transposed) or 2 (both)");
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TORCH_CHECK(layout == 0 || x.dim() >= 2,
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"transposed quantize layouts need a 2D+ tensor");
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check_scale(scale, x);
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check_fp8_device(x);
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const at::cuda::OptionalCUDAGuard guard(x.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto input = x.contiguous();
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auto out_opts = input.options().dtype(
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fmt ? torch::kFloat8_e5m2 : torch::kFloat8_e4m3fn);
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auto amax = torch::zeros({1}, input.options().dtype(torch::kFloat32));
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FP8QuantizeParams p;
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p.input_ptr = input.data_ptr();
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p.scale = scale.data_ptr<float>();
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p.amax = amax.data_ptr<float>();
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p.total = static_cast<int>(input.numel());
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p.out_layout = static_cast<int>(layout);
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p.rows = static_cast<int>(input.size(-2));
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p.cols = static_cast<int>(input.size(-1));
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torch::Tensor output, output_t;
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if (layout == 0 || layout == 2) {
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output = torch::empty_like(input, out_opts);
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p.output_ptr = output.data_ptr();
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}
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if (layout >= 1) {
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output_t = torch::empty({input.size(-1), input.size(-2)}, out_opts);
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p.output_transposed_ptr = output_t.data_ptr();
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}
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const bool e5m2 = fmt == static_cast<int64_t>(FP8Format::E5M2);
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if (layout != 0)
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launch_quantize_for<true>(input, p, e5m2, stream.stream());
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else
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launch_quantize_for<false>(input, p, e5m2, stream.stream());
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C10_CUDA_CHECK(cudaGetLastError());
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if (layout == 2) return py::make_tuple(output, output_t, amax);
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return py::make_tuple(layout == 1 ? output_t : output, amax);
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}
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torch::Tensor mm_fp8(torch::Tensor a, torch::Tensor b, torch::Tensor scale,
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int64_t trans_a, int64_t trans_b, torch::Tensor bias) {
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TORCH_CHECK(a.is_cuda() && b.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(a.scalar_type() == torch::kFloat8_e4m3fn ||
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a.scalar_type() == torch::kFloat8_e5m2,
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"a and b must be fp8");
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TORCH_CHECK(a.scalar_type() == b.scalar_type(), "a and b must share format");
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TORCH_CHECK((a.dim() == 2 || a.dim() == 3) &&
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(b.dim() == 2 || b.dim() == 3),
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"a and b must be 2D or 3D (batched)");
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TORCH_CHECK(a.device() == b.device(), "a and b must share device");
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check_scale(scale, a);
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check_fp8_device(a);
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const at::cuda::OptionalCUDAGuard guard(a.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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// Batched operands follow matmul broadcast rules: 2D acts as a batch
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// of 1; a size-1 batch broadcasts across the other side (stride 0).
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const int64_t batch_a = a.dim() == 3 ? a.size(0) : 1;
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const int64_t batch_b = b.dim() == 3 ? b.size(0) : 1;
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TORCH_CHECK(batch_a == batch_b || batch_a == 1 || batch_b == 1,
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"batch dim mismatch (got ", batch_a, " and ", batch_b, ")");
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const int64_t batch = std::max(batch_a, batch_b);
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TORCH_CHECK(batch <= 65535, "batch dim exceeds the grid.z launch limit");
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torch::Tensor a_st, b_st;
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int64_t a_ld, b_ld, a_bstride, b_bstride;
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const bool tag_a =
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resolve_operand(a, trans_a != 0, a_ld, a_bstride, a_st);
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const bool tag_b =
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resolve_operand(b, trans_b != 0, b_ld, b_bstride, b_st);
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// GEMM dims from the user flags; storage layout never swaps them.
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const int64_t m = trans_a ? a.size(-1) : a.size(-2);
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const int64_t k = trans_a ? a.size(-2) : a.size(-1);
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const int64_t n = trans_b ? b.size(-2) : b.size(-1);
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TORCH_CHECK(k == (trans_b ? b.size(-1) : b.size(-2)), "inner dim mismatch");
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const bool batched_out = a.dim() == 3 || b.dim() == 3;
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torch::Tensor output =
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batched_out
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? torch::empty({batch, m, n}, a.options().dtype(torch::kBFloat16))
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: torch::empty({m, n}, a.options().dtype(torch::kBFloat16));
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FP8Params p;
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p.a_ptr = a_st.data_ptr();
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p.b_ptr = b_st.data_ptr();
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p.out_ptr = output.data_ptr();
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p.scale = scale.data_ptr<float>();
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p.m = static_cast<int>(m);
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p.n = static_cast<int>(n);
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p.k = static_cast<int>(k);
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p.a_ld = static_cast<int>(a_ld);
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p.b_ld = static_cast<int>(b_ld);
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// Fused epilogue bias (bf16, broadcast over rows and batches). An
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// undefined or 0-element tensor keeps the plain scaled output.
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if (bias.defined() && bias.numel() > 0) {
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TORCH_CHECK(bias.is_cuda() && bias.scalar_type() == torch::kBFloat16,
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"fp8 gemm bias must be a CUDA bf16 tensor");
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TORCH_CHECK(bias.dim() == 1 && bias.size(0) == n,
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"fp8 gemm bias must be 1D of length n=", n);
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TORCH_CHECK(bias.is_contiguous(), "fp8 gemm bias must be contiguous");
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p.bias_ptr = bias.data_ptr();
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}
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p.batch = static_cast<int>(batch);
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p.a_batch_stride = (batch_a == 1 && batch > 1) ? 0 : a_bstride;
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p.b_batch_stride = (batch_b == 1 && batch > 1) ? 0 : b_bstride;
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p.out_batch_stride = m * n;
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if (a.scalar_type() == torch::kFloat8_e4m3fn)
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gemm<FP8Format::E4M3>(p, stream.stream(), tag_a, tag_b);
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else
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gemm<FP8Format::E5M2>(p, stream.stream(), tag_a, tag_b);
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C10_CUDA_CHECK(cudaGetLastError());
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return output;
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}
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// mm_fp8 binding: Python None and an omitted argument both mean "no bias",
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// so every Python layer can pass its bias argument through untouched.
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PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
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m.def("quantize", &quantize, py::arg("x"), py::arg("scale"),
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py::arg("fmt"), py::arg("layout") = 0);
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m.def(
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"mm_fp8",
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[](torch::Tensor a, torch::Tensor b, torch::Tensor scale,
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int64_t trans_a, int64_t trans_b, py::object bias) {
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torch::Tensor t;
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if (!bias.is_none()) {
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// (py::isinstance<torch::Tensor> is false for real tensors
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// here — torch's caster registers no pybind type info — so
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// validate by attempting the cast itself.)
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try {
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t = bias.cast<torch::Tensor>();
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} catch (const py::cast_error&) {
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TORCH_CHECK(false, "bias must be a torch.Tensor or None");
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}
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}
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return mm_fp8(a, b, scale, trans_a, trans_b, t);
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},
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py::arg("a"), py::arg("b"), py::arg("scale"), py::arg("trans_a") = 0,
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py::arg("trans_b") = 0, py::arg("bias") = py::none());
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}
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