ViperEkura
7aa5ed09d9
- Merge cos/sin into single freqs_cis tensor [batch, seq, dim/2, 2] throughout the pipeline: RotaryEmbedding buffer, forward return type, apply_rotary_emb signature, CUDA kernel interface - CUDA kernel now takes freqs_cis directly and reads cos/sin via stride offset internally, eliminating Python-side slice/copy overhead - Kernel interface: rotary_emb(x, freqs_cis) replaces rotary_emb(x, cos, sin) - All call sites pass rotary_emb as Tensor (was tuple), type annotations consistent - Update build threads from 8 to 16 - Fix all docs: get-started, inference, training, cuda_kernels, architecture, internals — reflect new rotary interface, KVCache fields, rotary backend dispatch, .so path, kernel registry count, file layout
176 lines
7.5 KiB
Markdown
176 lines
7.5 KiB
Markdown
# CUDA Kernels
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AstrAI includes optional custom CUDA kernels for attention and rotary embedding. These are built when `nvcc` is available and CUDA is detected, and are dispatched via the `CudaBackend` attention backend or auto-dispatched for rotary.
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## Overview
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| Kernel | File | Description |
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|--------|------|-------------|
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| `attn_decode` | `attn_decode.cu` | GQA decode attention (split-KV) |
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| `attn_prefill` | `attn_prefill.cu` | GQA prefill attention (split-Q) |
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| `attn_paged_decode` | `attn_paged_decode.cu` | Paged KV cache decode attention |
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| `rotary_emb` | `rotary_emb.cu` | Fused rotary embedding (cos/sin lookup + rotation) |
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Additionally, optimized `.cuh` variants with tensor-core MMA (Matrix Multiply-Accumulate) exist:
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| Variant | File | Optimization |
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|---------|------|--------------|
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| Split-KV MMA decode | `attn_decode_split_kv_mma.cuh` | Split KV across warps + MMA (sm_80+) |
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| Split-Q MMA prefill | `attn_prefill_split_q_mma.cuh` | Split Q across warps + MMA (sm_80+) |
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| Paged split-KV MMA decode | `attn_paged_decode_split_kv_mma.cuh` | Paged cache + split-KV + MMA |
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### Rotary Embedding Kernel
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The `rotary_emb` kernel (`csrc/kernels/rotary_emb.cu`) fuses cos/sin lookup and rotation into a single kernel:
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- One thread per (head, dim-pair), vectorized `__nv_bfloat162` load/store
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- f32 cos/sin input, bf16 compute and output
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- 256-thread blocks, grid-stride loop
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- Auto-dispatched via `apply_rotary_emb` in `astrai/extension/rotary_backend.py` (CUDA when available + inference mode, else torch complex-multiply fallback)
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- No context-manager backend needed — rotary is backend-agnostic, both attention backends benefit
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Standalone benchmark vs torch complex-multiply (48 calls = 24 layers × q+k): 6-9x faster, max diff 0 (decode) to 3e-2 (large prefill, bf16).
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## Build System
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### Auto-detection
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Kernels are built when **both** of these conditions are met:
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1. `nvcc` is available on `PATH`
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2. `torch.cuda.is_available()` returns `True`
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Unless `CSRC_KERNELS=false` is set explicitly.
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### Manual build
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```bash
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# During install
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CSRC_KERNELS=true pip install -e . --no-build-isolation
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# Rebuild after editing .cu/.cuh files
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CSRC_KERNELS=true python setup.py build_ext --inplace
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# Output: astrai/extension/lib/*.so
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```
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### Architecture flags
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`csrc/build.py` auto-detects the GPU compute capability and generates the appropriate `nvcc` gencode flag:
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- **sm_80+** (Ampere and later): enables tensor-core MMA path (`mma.sync.m16n8k16.bf16`)
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- **Below sm_80**: adds `-DASTRAI_NO_MMA` to disable the MMA path at compile time
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### Build configuration
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```
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NVCC_FLAGS = -O3 --expt-relaxed-constexpr --use_fast_math
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--ptxas-options=-O3,-v --extra-device-vectorization --threads=8
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```
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The `REGISTRY` in `csrc/build.py` lists all registered kernels (currently 4). Each entry maps a kernel name to its source files and build flags.
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## Attention Backend
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`astrai/extension/attention_backend.py` provides the backend abstraction:
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- **`AttentionBackend`** (ABC): `fwd_decode` / `fwd_prefill` abstract methods, `forward` dispatches by q_len
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- **`TorchNativeBackend`**: SDPA with indirect KV cache gather (default)
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- **`CudaBackend`**: CUDA kernel dispatch — decode via `attn_paged_decode` (page_size=1), prefill via `attn_prefill`
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Select a backend via context manager (mirrors `torch.nn.attention.sdpa_kernel`):
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```python
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from astrai.extension import attn_backend, ATTN_BACKEND
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with attn_backend(ATTN_BACKEND.CUDA):
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engine.generate("hello")
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```
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`CudaBackend` falls back to `TorchNativeBackend` when a kernel is not available.
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### Rotary Backend
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`astrai/extension/rotary_backend.py` provides `apply_rotary_emb(x, (cos, sin))` with auto-dispatch:
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- **CUDA path**: calls `rotary_emb` kernel directly when available, input is bf16 on CUDA, and `torch.is_grad_enabled()` is `False` (inference)
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- **Torch fallback**: complex multiply (`torch.view_as_complex` → `torch.complex` multiply → `torch.view_as_real`), used during training (supports autograd) or when kernel unavailable
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No context-manager switching needed — the dispatch is automatic per call.
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## Python Wrappers
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`astrai/extension/attention_ops.py` provides Python wrappers for each compiled attention kernel. Each wrapper calls its CUDA kernel directly and raises `RuntimeError` if the `.so` is not available. Fallback to torch SDPA is handled by the attention backend, not the wrapper functions.
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`astrai/extension/rotary_ops.py` provides the wrapper for the rotary embedding kernel. Fallback to torch complex multiply is handled by `rotary_backend.py`.
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Interface (all functions):
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```
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is_causal: True = causal mask; False = non-causal
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mask: 2D [batch, kv_len] or 3D [batch, q_len, kv_len] (bool, True=keep)
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```
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Layout convention: all q/k/v are `[batch, seq_len, n_heads, head_dim]` (blhd). Scale is always `1/sqrt(head_dim)`.
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## Standalone Testing
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Each `csrc/tests/*.cu` file has the `nvcc` compile command in its header comment. Example:
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```bash
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nvcc -I csrc -arch=sm_89 -O3 --use_fast_math \
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--ptxas-options=-O3,-v --extra-device-vectorization \
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csrc/tests/attn_decode_test.cu -o /tmp/test && /tmp/test
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```
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Test files:
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- `attn_decode_test.cu` — basic decode kernel
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- `attn_paged_decode_test.cu` — paged decode kernel
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- `attn_prefill_test.cu` — prefill kernel
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## Benchmarks
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Hardware: NVIDIA L20 (sm_89, 46 GB), CUDA 12.8, driver 570.86.
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Reproduce:
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```bash
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nvcc -I csrc -arch=sm_89 -O3 --use_fast_math \
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--ptxas-options=-O3,-v --extra-device-vectorization \
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csrc/tests/attn_<name>_test.cu -o /tmp/test && /tmp/test
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```
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## Known Optimization Targets
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- **Decode D=256**: spill eliminated (BC=16 + STAGES=2), but still 248 regs — further tiling could help.
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- **Prefill single-batch**: bandwidth low (22 GB/s at q=kv=2048) — compute-bound at ~94 TFLOP/s (near L20 bf16 ceiling ~193 TFLOP/s for non-causal).
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- **Decode single-batch**: bandwidth low (113 GB/s at kv=512, 13% of 864 GB/s theoretical) — small kv underutilizes SMs despite split-KV; scales to 757 GB/s (88%) at B=16+.
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## File Layout
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```
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csrc/
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├── build.py # Build system: REGISTRY, _arch_flags, nvcc flags
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├── kernels/
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│ ├── attn_common.h # Shared attention params (AttentionParams, PagedAttentionParams)
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│ ├── attn_decode.cu # Basic decode kernel (registered)
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│ ├── attn_prefill.cu # Basic prefill kernel (registered)
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│ ├── attn_paged_decode.cu # Paged decode kernel (registered)
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│ ├── rotary_emb.cu # Fused rotary embedding kernel (registered)
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│ ├── attn_decode_split_kv.cuh # Split-KV variant
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│ ├── attn_decode_split_kv_mma.cuh # Split-KV + MMA variant
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│ ├── attn_prefill_split_q.cuh # Split-Q variant
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│ ├── attn_prefill_split_q_mma.cuh # Split-Q + MMA variant
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│ ├── attn_paged_decode_split_kv.cuh # Paged + split-KV variant
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│ ├── attn_paged_decode_split_kv_mma.cuh # Paged + split-KV + MMA variant
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│ ├── attn_dispatchers.cuh # Kernel dispatch macros
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│ ├── attn_entry_utils.cuh # Entry point helpers
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│ ├── attn_mma_utils.cuh # MMA utilities
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│ └── attn_warp_utils.cuh # Warp-level utilities
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└── tests/
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├── test_utils.cuh # Shared test utilities
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├── attn_decode_test.cu # Decode kernel test
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├── attn_paged_decode_test.cu # Paged decode test
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└── attn_prefill_test.cu # Prefill kernel test
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```
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Compiled `.so` files are placed in `astrai/extension/lib/`, separate from Python source files.
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> Document Update Time: 2026-07-31
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