ViperEkura
5244f1a8fc
- per-tensor scales applied inside cublasLt via A_SCALE/B_SCALE - delayed scaling: weight amax history ring, refresh every 16 steps - quantize kernels emit atomic amax, device-side scale updates - fp8_autocast context toggles aten::linear dispatch like torch.autocast - fallback to bf16 when M/N not 16-aligned (fp8 gemm constraint) - x/g scales delayed one step, reuse free atomic amax (no abs/max reduce)
442 lines
20 KiB
Plaintext
442 lines
20 KiB
Plaintext
// FP8 e4m3 matrix multiply via cuBLASLt (sm89 TN layout).
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//
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// cuBLASLt exposes fp8 kernels only for op(A)=T, op(B)=N on Ada; we exploit
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// the identity: row-major a[M,K] == A^T as col-major [K,M] (zero copy), and
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// row-major wT[N,K] == B as col-major [K,N] (zero copy). The col-major
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// result D[M,N] is C^T in row-major terms, so we transpose the output once.
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//
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// Inputs arrive pre-scaled fp8 e4m3 tensors; output is unscaled fp32.
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#include <torch/extension.h>
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#include <ATen/cuda/CUDAContext.h>
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#include <c10/cuda/CUDAGuard.h>
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#include <cublasLt.h>
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#include <cuda_fp8.h>
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#include <cstdint>
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#include <mutex>
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#include <unordered_map>
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static std::recursive_mutex g_mutex;
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static cublasLtHandle_t g_handle = nullptr;
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static cublasLtMatmulDesc_t g_desc = nullptr;
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static cublasLtMatrixLayout_t g_layout_a = nullptr;
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static cublasLtMatrixLayout_t g_layout_b = nullptr;
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static cublasLtMatrixLayout_t g_layout_c = nullptr;
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static cublasLtMatmulPreference_t g_pref = nullptr;
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static void* g_workspace = nullptr;
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static size_t g_ws_size = 0;
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struct ShapeKey {
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int64_t m;
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int64_t k;
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int64_t n;
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bool operator==(const ShapeKey& other) const {
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return m == other.m && k == other.k && n == other.n;
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}
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};
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struct ShapeKeyHash {
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size_t operator()(const ShapeKey& s) const {
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size_t h = std::hash<int64_t>()(s.m);
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h ^= std::hash<int64_t>()(s.k) + 0x9e3779b9 + (h << 6) + (h >> 2);
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h ^= std::hash<int64_t>()(s.n) + 0x9e3779b9 + (h << 6) + (h >> 2);
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return h;
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}
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};
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using AlgoCache = std::unordered_map<ShapeKey, cublasLtMatmulAlgo_t, ShapeKeyHash>;
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static void create_matmul_config(cublasLtMatmulDesc_t* desc,
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cublasLtMatrixLayout_t* layout_a,
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cublasLtMatrixLayout_t* layout_b,
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cublasLtMatrixLayout_t* layout_c) {
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cublasOperation_t ta = CUBLAS_OP_T, tb = CUBLAS_OP_N;
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TORCH_CHECK(cublasLtMatmulDescCreate(desc, CUBLAS_COMPUTE_32F, CUDA_R_32F) ==
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CUBLAS_STATUS_SUCCESS);
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TORCH_CHECK(cublasLtMatmulDescSetAttribute(
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*desc, CUBLASLT_MATMUL_DESC_TRANSA, &ta, sizeof(ta)) ==
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CUBLAS_STATUS_SUCCESS);
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TORCH_CHECK(cublasLtMatmulDescSetAttribute(
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*desc, CUBLASLT_MATMUL_DESC_TRANSB, &tb, sizeof(tb)) ==
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CUBLAS_STATUS_SUCCESS);
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TORCH_CHECK(cublasLtMatrixLayoutCreate(layout_a, CUDA_R_8F_E4M3, 1, 1, 1) ==
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CUBLAS_STATUS_SUCCESS);
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TORCH_CHECK(cublasLtMatrixLayoutCreate(layout_b, CUDA_R_8F_E4M3, 1, 1, 1) ==
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CUBLAS_STATUS_SUCCESS);
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TORCH_CHECK(cublasLtMatrixLayoutCreate(layout_c, CUDA_R_16BF, 1, 1, 1) ==
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CUBLAS_STATUS_SUCCESS);
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}
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static void ensure_cublas_lt() {
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std::lock_guard<std::recursive_mutex> lock(g_mutex);
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if (g_handle) {
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return;
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}
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TORCH_CHECK(cublasLtCreate(&g_handle) == CUBLAS_STATUS_SUCCESS);
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create_matmul_config(&g_desc, &g_layout_a, &g_layout_b, &g_layout_c);
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TORCH_CHECK(cublasLtMatmulPreferenceCreate(&g_pref) == CUBLAS_STATUS_SUCCESS);
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size_t ws = 16 * 1024 * 1024;
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TORCH_CHECK(cublasLtMatmulPreferenceSetAttribute(
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g_pref, CUBLASLT_MATMUL_PREF_MAX_WORKSPACE_BYTES, &ws, sizeof(ws)) ==
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CUBLAS_STATUS_SUCCESS);
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}
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static cublasStatus_t get_algo_cached(int64_t m, int64_t k, int64_t n,
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AlgoCache* cache,
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cublasLtMatmulAlgo_t* algo);
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static void fp8_gemm_into(torch::Tensor lhs, torch::Tensor rhs, torch::Tensor out,
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int64_t m, int64_t k, int64_t n,
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const float* a_scale, const float* b_scale,
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cudaStream_t stream);
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static const float k_scale_one = 1.0f;
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static void set_layout(cublasLtMatrixLayout_t layout, int64_t rows, int64_t cols,
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int64_t ld) {
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TORCH_CHECK(cublasLtMatrixLayoutSetAttribute(layout, CUBLASLT_MATRIX_LAYOUT_ROWS,
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&rows, sizeof(rows)) ==
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CUBLAS_STATUS_SUCCESS);
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TORCH_CHECK(cublasLtMatrixLayoutSetAttribute(layout, CUBLASLT_MATRIX_LAYOUT_COLS,
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&cols, sizeof(cols)) ==
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CUBLAS_STATUS_SUCCESS);
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TORCH_CHECK(cublasLtMatrixLayoutSetAttribute(layout, CUBLASLT_MATRIX_LAYOUT_LD,
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&ld, sizeof(ld)) ==
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CUBLAS_STATUS_SUCCESS);
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}
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torch::Tensor fp8_mm(torch::Tensor a, torch::Tensor b) {
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TORCH_CHECK(a.is_cuda() && b.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(a.scalar_type() == torch::kFloat8_e4m3fn, "a must be float8_e4m3fn");
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TORCH_CHECK(b.scalar_type() == torch::kFloat8_e4m3fn, "b must be float8_e4m3fn");
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TORCH_CHECK(a.dim() == 2 && b.dim() == 2, "2D tensors required");
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const at::cuda::OptionalCUDAGuard guard(a.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto a_c = a.contiguous();
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auto b_c = b.contiguous();
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int64_t m = a_c.size(0), k = a_c.size(1), n = b_c.size(0);
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TORCH_CHECK(b_c.size(1) == k, "inner dim mismatch");
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auto buf = torch::empty({m, n}, a_c.options().dtype(torch::kBFloat16));
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ensure_cublas_lt();
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fp8_gemm_into(a_c, b_c, buf, m, k, n, &k_scale_one, &k_scale_one,
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stream.stream());
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return buf;
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}
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// ---------------------------------------------------------------------------
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// Quantize: bf16 * scale_inv -> fp8, one atomicMax amax per kernel call.
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// amax_ptr must be zeroed before launch; float-bits atomicMax works because
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// |v| >= 0 has a monotonic IEEE bit pattern.
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// ---------------------------------------------------------------------------
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template <typename T8>
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__device__ __forceinline__ T8 cast_fp8(float v);
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template <>
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__device__ __forceinline__ __nv_fp8_e4m3 cast_fp8<__nv_fp8_e4m3>(float v) {
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return __nv_fp8_e4m3(v);
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}
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template <>
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__device__ __forceinline__ __nv_fp8_e5m2 cast_fp8<__nv_fp8_e5m2>(float v) {
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return __nv_fp8_e5m2(v);
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}
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template <typename T8>
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__global__ void quantize_kernel(const __nv_bfloat16* __restrict__ src,
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const float* __restrict__ scale_inv,
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T8* __restrict__ dst,
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float* __restrict__ amax_ptr, int64_t n) {
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int64_t i = blockIdx.x * (int64_t)blockDim.x + threadIdx.x;
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float amax = 0.f;
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if (i < n) {
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float v = __bfloat162float(src[i]) * *scale_inv;
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dst[i] = cast_fp8<T8>(v);
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amax = fabsf(v);
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}
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for (int off = 16; off; off >>= 1)
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amax = fmaxf(amax, __shfl_xor_sync(0xffffffffu, amax, off));
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__shared__ float sm[8];
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if ((threadIdx.x & 31) == 0) sm[threadIdx.x >> 5] = amax;
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__syncthreads();
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if (threadIdx.x == 0) {
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float m = 0.f;
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for (int w = 0; w < blockDim.x / 32; ++w) m = fmaxf(m, sm[w]);
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atomicMax(reinterpret_cast<unsigned*>(amax_ptr), __float_as_uint(m));
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}
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}
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// Same but with a transpose (rows x cols bf16 row-major -> fp8 [cols, rows]).
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template <typename T8>
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__global__ void transpose_quantize_kernel(
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const __nv_bfloat16* __restrict__ src, const float* __restrict__ scale_inv,
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T8* __restrict__ dst, float* __restrict__ amax_ptr, int64_t rows,
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int64_t cols) {
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__shared__ T8 tile[32][33];
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int64_t x = blockIdx.x * 32 + threadIdx.x;
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int64_t y = blockIdx.y * 32 + threadIdx.y;
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float amax = 0.f;
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for (int j = 0; j < 32; j += 8) {
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if (x < cols && y + j < rows) {
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float v = __bfloat162float(src[(y + j) * cols + x]) * *scale_inv;
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tile[threadIdx.y + j][threadIdx.x] = cast_fp8<T8>(v);
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amax = fmaxf(amax, fabsf(v));
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}
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}
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__syncthreads();
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x = blockIdx.y * 32 + threadIdx.x;
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y = blockIdx.x * 32 + threadIdx.y;
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for (int j = 0; j < 32; j += 8) {
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if (x < rows && y + j < cols) {
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dst[(y + j) * rows + x] = tile[threadIdx.x][threadIdx.y + j];
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}
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}
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for (int off = 16; off; off >>= 1)
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amax = fmaxf(amax, __shfl_xor_sync(0xffffffffu, amax, off));
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__shared__ float sm[8];
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if ((threadIdx.x & 31) == 0) sm[threadIdx.x >> 5] = amax;
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__syncthreads();
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if (threadIdx.x == 0) {
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float m = 0.f;
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for (int w = 0; w < blockDim.x / 32; ++w) m = fmaxf(m, sm[w]);
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atomicMax(reinterpret_cast<unsigned*>(amax_ptr), __float_as_uint(m));
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}
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}
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__global__ void bias_add_bf16_kernel(
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__nv_bfloat16* __restrict__ dst, const __nv_bfloat16* __restrict__ bias,
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int64_t total, int64_t n) {
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// GEMM and output use the same row-major [M,N] layout.
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int64_t idx = blockIdx.x * (int64_t)blockDim.x + threadIdx.x;
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if (idx >= total) return;
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float v = __bfloat162float(dst[idx]);
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dst[idx] = __float2bfloat16(v + __bfloat162float(bias[idx % n]));
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}
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static cublasStatus_t get_algo_cached(int64_t m, int64_t k, int64_t n,
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AlgoCache* cache,
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cublasLtMatmulAlgo_t* algo) {
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std::lock_guard<std::recursive_mutex> lock(g_mutex);
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ShapeKey key{m, k, n};
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auto it = cache->find(key);
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if (it != cache->end()) {
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*algo = it->second;
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return CUBLAS_STATUS_SUCCESS;
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}
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cublasLtMatmulHeuristicResult_t heur;
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int returned = 0;
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cublasStatus_t st = cublasLtMatmulAlgoGetHeuristic(
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g_handle, g_desc, g_layout_a, g_layout_b, g_layout_c, g_layout_c, g_pref, 1,
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&heur, &returned);
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if (st != CUBLAS_STATUS_SUCCESS || returned == 0)
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return CUBLAS_STATUS_NOT_SUPPORTED;
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if (heur.workspaceSize > g_ws_size) {
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if (g_workspace) cudaFree(g_workspace);
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TORCH_CHECK(cudaMalloc(&g_workspace, heur.workspaceSize) == cudaSuccess);
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g_ws_size = heur.workspaceSize;
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}
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cache->emplace(key, heur.algo);
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*algo = heur.algo;
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return CUBLAS_STATUS_SUCCESS;
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}
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static void fp8_gemm_into(torch::Tensor lhs, torch::Tensor rhs, torch::Tensor out,
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int64_t m, int64_t k, int64_t n,
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const float* a_scale, const float* b_scale,
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cudaStream_t stream) {
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std::lock_guard<std::recursive_mutex> lock(g_mutex);
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set_layout(g_layout_a, k, n, k); // param A = rhs (op=T -> [N,K])
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set_layout(g_layout_b, k, m, k); // param B = lhs (op=N -> [K,M])
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set_layout(g_layout_c, n, m, n); // col-major [N,M] == row-major [M,N]
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// Per-tensor FP32 scales applied inside the GEMM:
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// D = alpha * A_SCALE * B_SCALE * A * B (alpha = 1).
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TORCH_CHECK(cublasLtMatmulDescSetAttribute(
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g_desc, CUBLASLT_MATMUL_DESC_A_SCALE_POINTER, &a_scale,
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sizeof(a_scale)) == CUBLAS_STATUS_SUCCESS);
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TORCH_CHECK(cublasLtMatmulDescSetAttribute(
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g_desc, CUBLASLT_MATMUL_DESC_B_SCALE_POINTER, &b_scale,
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sizeof(b_scale)) == CUBLAS_STATUS_SUCCESS);
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float alpha = 1.0f, beta = 0.0f;
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static AlgoCache cache;
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cublasLtMatmulAlgo_t algo;
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cublasStatus_t st = get_algo_cached(m, k, n, &cache, &algo);
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TORCH_CHECK(st == CUBLAS_STATUS_SUCCESS,
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"cublasLtMatmulAlgoGetHeuristic failed: ", cublasLtGetStatusName(st));
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st = cublasLtMatmul(g_handle, g_desc, &alpha, rhs.data_ptr(), g_layout_a,
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lhs.data_ptr(), g_layout_b, &beta, out.data_ptr(), g_layout_c,
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out.data_ptr(), g_layout_c, &algo, g_workspace, g_ws_size,
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stream);
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TORCH_CHECK(st == CUBLAS_STATUS_SUCCESS,
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"cublasLtMatmul failed: ", cublasLtGetStatusName(st));
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}
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// ---------------------------------------------------------------------------
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// Scaled FP8 linear forward: quantize x/w with per-tensor scales -> cublasLt
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// GEMM (scales applied inside) -> bias in-place -> bf16 [..., N].
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// sx/sw: f32 scale tensors (device scalars); sx_inv/sw_inv: 1/scale.
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// amax_x/amax_w: f32 buffers receiving max-abs of the quantized tensors.
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// ---------------------------------------------------------------------------
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torch::Tensor fp8_linear_forward_scaled(torch::Tensor x, torch::Tensor w,
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torch::Tensor bias, torch::Tensor sx,
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torch::Tensor sw, torch::Tensor sx_inv,
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torch::Tensor sw_inv,
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torch::Tensor amax_x,
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torch::Tensor amax_w) {
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TORCH_CHECK(x.is_cuda() && w.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(x.dtype() == torch::kBFloat16 && w.dtype() == torch::kBFloat16,
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"x and w must be bf16");
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const at::cuda::OptionalCUDAGuard guard(x.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto x_c = x.reshape({-1, w.size(1)}).contiguous();
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auto w_c = w.contiguous();
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int64_t m = x_c.size(0), k = x_c.size(1), n = w_c.size(0);
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TORCH_CHECK(w_c.size(1) == k, "inner dim mismatch");
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ensure_cublas_lt();
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const float* sx_ptr = sx.data_ptr<float>();
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const float* sw_ptr = sw.data_ptr<float>();
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const float* sxi_ptr = sx_inv.data_ptr<float>();
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const float* swi_ptr = sw_inv.data_ptr<float>();
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float* amax_x_ptr = amax_x.data_ptr<float>();
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float* amax_w_ptr = amax_w.data_ptr<float>();
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C10_CUDA_CHECK(cudaMemsetAsync(amax_x_ptr, 0, sizeof(float), stream.stream()));
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C10_CUDA_CHECK(cudaMemsetAsync(amax_w_ptr, 0, sizeof(float), stream.stream()));
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auto x8 = torch::empty({m, k}, x_c.options().dtype(torch::kFloat8_e4m3fn));
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auto w8 = torch::empty({n, k}, w_c.options().dtype(torch::kFloat8_e4m3fn));
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int64_t block = 256;
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quantize_kernel<__nv_fp8_e4m3>
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<<<(unsigned)((m * k + block - 1) / block), block, 0, stream.stream()>>>(
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reinterpret_cast<const __nv_bfloat16*>(x_c.data_ptr()), sxi_ptr,
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reinterpret_cast<__nv_fp8_e4m3*>(x8.data_ptr()), amax_x_ptr, m * k);
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quantize_kernel<__nv_fp8_e4m3>
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<<<(unsigned)((n * k + block - 1) / block), block, 0, stream.stream()>>>(
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reinterpret_cast<const __nv_bfloat16*>(w_c.data_ptr()), swi_ptr,
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reinterpret_cast<__nv_fp8_e4m3*>(w8.data_ptr()), amax_w_ptr, n * k);
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C10_CUDA_CHECK(cudaGetLastError());
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auto out = torch::empty({m, n}, x_c.options());
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fp8_gemm_into(x8, w8, out, m, k, n, sw_ptr, sx_ptr, stream.stream());
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if (bias.defined() && bias.numel() > 0) {
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TORCH_CHECK(bias.scalar_type() == torch::kBFloat16 && bias.numel() == n,
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"bias must be bf16 with shape [N]");
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bias_add_bf16_kernel<<<(unsigned)((m * n + block - 1) / block), block, 0, stream>>>(
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reinterpret_cast<__nv_bfloat16*>(out.data_ptr()),
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reinterpret_cast<const __nv_bfloat16*>(bias.data_ptr()), m * n, n);
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C10_CUDA_CHECK(cudaGetLastError());
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}
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std::vector<int64_t> shape(x.sizes().begin(), x.sizes().end() - 1);
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shape.push_back(n);
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return out.reshape(shape);
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}
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// ---------------------------------------------------------------------------
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// Scaled FP8 linear backward: dX = g @ W, dW = g^T @ X, dB = sum(g).
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// Scales: g uses sg (immediate), w/x reuse the forward scales.
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// ---------------------------------------------------------------------------
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std::tuple<torch::Tensor, torch::Tensor, torch::Tensor> fp8_linear_backward_scaled(
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torch::Tensor g, torch::Tensor x, torch::Tensor w,
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std::vector<int64_t> masks, torch::Tensor sg, torch::Tensor sw,
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torch::Tensor sx, torch::Tensor sg_inv, torch::Tensor sw_inv,
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torch::Tensor sx_inv, torch::Tensor amax_g) {
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const at::cuda::OptionalCUDAGuard guard(g.device());
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TORCH_CHECK(g.dtype() == torch::kBFloat16 && x.dtype() == torch::kBFloat16 &&
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w.dtype() == torch::kBFloat16,
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"g, x, and w must be bf16");
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auto stream = at::cuda::getCurrentCUDAStream();
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auto g_c = g.reshape({-1, w.size(0)}).contiguous();
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auto x_c = x.reshape({-1, x.size(-1)}).contiguous();
|
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auto w_c = w.contiguous();
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int64_t m = g_c.size(0);
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int64_t n = w.size(0);
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int64_t k = w.size(1);
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TORCH_CHECK(x_c.size(0) == m && x_c.size(1) == k && g_c.size(1) == n,
|
|
"backward shape mismatch");
|
|
|
|
auto grad_input = torch::empty_like(x);
|
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auto grad_weight = torch::empty_like(w);
|
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auto grad_bias = torch::empty({0}, g_c.options().dtype(g.dtype()));
|
|
ensure_cublas_lt();
|
|
|
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const float* sg_ptr = sg.data_ptr<float>();
|
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const float* sw_ptr = sw.data_ptr<float>();
|
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const float* sx_ptr = sx.data_ptr<float>();
|
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const float* sgi_ptr = sg_inv.data_ptr<float>();
|
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const float* swi_ptr = sw_inv.data_ptr<float>();
|
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const float* sxi_ptr = sx_inv.data_ptr<float>();
|
|
float* amax_g_ptr = amax_g.data_ptr<float>();
|
|
C10_CUDA_CHECK(cudaMemsetAsync(amax_g_ptr, 0, sizeof(float), stream.stream()));
|
|
|
|
auto fp8_options = g_c.options().dtype(torch::kFloat8_e4m3fn);
|
|
auto g8 = torch::empty({m, n}, fp8_options);
|
|
auto gt8 = masks[1] ? torch::empty({n, m}, fp8_options) : torch::Tensor();
|
|
auto wt8 = masks[0] ? torch::empty({k, n}, fp8_options) : torch::Tensor();
|
|
auto xt8 = masks[1] ? torch::empty({k, m}, fp8_options) : torch::Tensor();
|
|
|
|
int64_t block = 256;
|
|
quantize_kernel<__nv_fp8_e4m3>
|
|
<<<(unsigned)((m * n + block - 1) / block), block, 0, stream.stream()>>>(
|
|
reinterpret_cast<const __nv_bfloat16*>(g_c.data_ptr()), sgi_ptr,
|
|
reinterpret_cast<__nv_fp8_e4m3*>(g8.data_ptr()), amax_g_ptr, m * n);
|
|
dim3 threads(32, 8);
|
|
if (masks[0]) {
|
|
dim3 blocks((k + 31) / 32, (n + 31) / 32);
|
|
transpose_quantize_kernel<__nv_fp8_e4m3>
|
|
<<<blocks, threads, 0, stream.stream()>>>(
|
|
reinterpret_cast<const __nv_bfloat16*>(w_c.data_ptr()), swi_ptr,
|
|
reinterpret_cast<__nv_fp8_e4m3*>(wt8.data_ptr()), amax_g_ptr,
|
|
n, k);
|
|
fp8_gemm_into(g8, wt8, grad_input.reshape({m, k}), m, n, k, sg_ptr,
|
|
sw_ptr, stream.stream());
|
|
}
|
|
if (masks[1]) {
|
|
dim3 g_blocks((n + 31) / 32, (m + 31) / 32);
|
|
dim3 x_blocks((k + 31) / 32, (m + 31) / 32);
|
|
transpose_quantize_kernel<__nv_fp8_e4m3>
|
|
<<<g_blocks, threads, 0, stream.stream()>>>(
|
|
reinterpret_cast<const __nv_bfloat16*>(g_c.data_ptr()), sgi_ptr,
|
|
reinterpret_cast<__nv_fp8_e4m3*>(gt8.data_ptr()), amax_g_ptr,
|
|
m, n);
|
|
transpose_quantize_kernel<__nv_fp8_e4m3>
|
|
<<<x_blocks, threads, 0, stream.stream()>>>(
|
|
reinterpret_cast<const __nv_bfloat16*>(x_c.data_ptr()), sxi_ptr,
|
|
reinterpret_cast<__nv_fp8_e4m3*>(xt8.data_ptr()), amax_g_ptr,
|
|
m, k);
|
|
fp8_gemm_into(gt8, xt8, grad_weight, n, m, k, sg_ptr, sx_ptr,
|
|
stream.stream());
|
|
}
|
|
C10_CUDA_CHECK(cudaGetLastError());
|
|
if (masks[2]) {
|
|
grad_bias = g_c.sum(0).to(g.dtype());
|
|
}
|
|
return std::tuple<torch::Tensor, torch::Tensor, torch::Tensor>(
|
|
grad_input, grad_weight, grad_bias);
|
|
}
|
|
|
|
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
|
|
m.def("fp8_mm", &fp8_mm, py::arg("a"), py::arg("b"),
|
|
"FP8 e4m3 GEMM: a[M,K] x b[N,K] -> bf16[M,N] (pre-scaled inputs)");
|
|
m.def("fp8_linear_forward_scaled", &fp8_linear_forward_scaled,
|
|
py::arg("x"), py::arg("w"), py::arg("bias"), py::arg("sx"),
|
|
py::arg("sw"), py::arg("sx_inv"), py::arg("sw_inv"),
|
|
py::arg("amax_x"), py::arg("amax_w"),
|
|
"Scaled FP8 linear forward: quantize with per-tensor scales + "
|
|
"cublasLt GEMM (scales applied inside) + bias -> bf16");
|
|
m.def("fp8_linear_backward_scaled", &fp8_linear_backward_scaled,
|
|
py::arg("g"), py::arg("x"), py::arg("w"), py::arg("masks"),
|
|
py::arg("sg"), py::arg("sw"), py::arg("sx"), py::arg("sg_inv"),
|
|
py::arg("sw_inv"), py::arg("sx_inv"), py::arg("amax_g"),
|
|
"Scaled FP8 linear backward: dX = g*sw @ W, dW = (g*sx)^T @ X, "
|
|
"dB = sum(g)");
|
|
}
|