- keep training attention on dense 4d tensors - use packed 3d tensors with KV cache for inference - extend CUDA rotary embedding to packed 3d inputs - adapt torch, CUDA and FlashAttention backend dispatch Benchmark: NVIDIA L20, BF16, 1B model, paged KV cache, CUDA Graph, prompt 512, generation 128 (median of 3 alternating runs) - batch 1: 234.5 -> 242.6 tok/s (1.034x, +3.4%) - batch 8: 1243.1 -> 1286.6 tok/s (1.035x, +3.5%)
184 lines
7.3 KiB
Plaintext
184 lines
7.3 KiB
Plaintext
#pragma once
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#include <cfloat>
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#include <cuda_bf16.h>
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#include "attn_common.h"
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#include "attn_layout_policies.cuh"
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#include "attn_mma_utils.cuh"
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#include "attn_warp_utils.cuh"
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// Split-K (FlashDecoding) tensor-core decode via GQA head-packing, unified
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// across contiguous and paged (SGLang flat-pool) K/V via the KV template
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// parameter. Decode has q_len == 1, so we pack G = q_head/kv_head query
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// heads into the M=16 rows of mma.sync.m16n8k16, turning G independent GEMVs
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// into a single GEMM that reuses each loaded K/V tile across all G heads.
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//
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// KV = ContigKV (dense tensors) or PagedKV (flat pool + req_to_token).
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// IsCausal and HasMask are compile-time bools — no runtime branch in the
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// inner compute loop.
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//
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// Traits = KernelTraits<HEAD_DIM, BC=16, WARPS=1, STAGES=2>.
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template <typename Traits, typename KV, bool IsCausal, bool HasMask>
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__global__ void attn_decode_split_kv_mma_kernel(AttentionParams<bf16> p) {
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const int lane = threadIdx.x;
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const int gid = lane >> 2;
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const int tid4 = lane & 3;
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const int pass = blockIdx.x / p.kv_head;
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const int kv_head = blockIdx.x % p.kv_head;
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const int batch = blockIdx.y;
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const int split = blockIdx.z;
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constexpr int MAX_G = 16;
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const int G_total = p.q_head / p.kv_head;
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const int g_begin = pass * MAX_G;
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const int G = min(MAX_G, G_total - g_begin);
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const int q_head0 = kv_head * G_total + g_begin;
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// Per-request seq_len (paged reads kv_indptr; contig uses p.kv_len).
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const int seq_len = KV::kv_len(p, batch);
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const KVContext kctx = KV::template make_ctx<Traits::HEAD_DIM>(p, batch, kv_head);
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// Double-buffered shared memory for K/V (no sQ needed)
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__shared__ __align__(16) bf16 sK[Traits::STAGES * Traits::BC * Traits::LD];
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__shared__ __align__(16) bf16 sV[Traits::STAGES * Traits::BC * Traits::LD];
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// Load Q directly from global into mma A-operand registers.
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const int q_base = KV::q_decode_base(p, batch, q_head0);
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const int qra = gid;
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const int qrb = gid + 8;
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const bool va = qra < G, vb = qrb < G;
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unsigned Qa[Traits::KD][4];
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load_q_mma_frags<Traits::KD>(p.q_ptr + q_base, p.q_h_stride, p.q_d_stride,
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qra, qrb, va, vb, tid4, Qa);
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float Oacc[Traits::DN8][4];
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#pragma unroll
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for (int j = 0; j < Traits::DN8; j++)
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Oacc[j][0] = Oacc[j][1] = Oacc[j][2] = Oacc[j][3] = 0.0f;
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float m0 = -FLT_MAX, m1 = -FLT_MAX, l0 = 0.0f, l1 = 0.0f;
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const int tiles_total = (seq_len + Traits::BC - 1) / Traits::BC;
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const int tiles_per_split = (tiles_total + p.num_splits - 1) / p.num_splits;
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const int ti_begin = split * tiles_per_split;
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const int ti_end = min(tiles_total, ti_begin + tiles_per_split);
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// ---- Load tile lambda: predicated cp.async (addressing via KV policy) ----
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auto load_tile = [&](int ti, int buf) {
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int kv0 = ti * Traits::BC;
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bf16* dK = sK + buf * Traits::BC * Traits::LD;
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bf16* dV = sV + buf * Traits::BC * Traits::LD;
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#pragma unroll
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for (int i = lane * Traits::VEC; i < Traits::TOTAL;
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i += Traits::NUM_THREADS * Traits::VEC) {
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int r = i / Traits::HEAD_DIM, d = i % Traits::HEAD_DIM;
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int kc = kv0 + r;
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bool valid = kc < seq_len;
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// All GQA passes consume new K/V directly. Only the first pass
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// persists it, so no cross-block synchronization is required.
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KVAddr a = KV::template decode_addr<Traits::VEC>(
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p, kctx, batch, kv_head, kc, d, valid, pass == 0);
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int off = r * Traits::LD + swiz_col(d, r, Traits::SWIZ_MASK);
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cp_async_16_pred(&dK[off], a.k, a.valid);
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cp_async_16_pred(&dV[off], a.v, a.valid);
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}
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cp_async_commit();
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};
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// ---- Multi-stage cp.async pipeline ----
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// Prologue loads STAGES tiles; each loop iteration waits only for the
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// oldest outstanding group (wait_group<STAGES-1>) so the STAGES-1 newer
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// tile loads stay in flight and overlap with the current tile's compute.
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constexpr int STAGES = Traits::STAGES;
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const int ntiles = ti_end - ti_begin;
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auto process_tile = [&](int it, int buf) {
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const bf16* bK = sK + buf * Traits::BC * Traits::LD;
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const bf16* bV = sV + buf * Traits::BC * Traits::LD;
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int kv0 = (ti_begin + it) * Traits::BC;
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float Sacc[Traits::NC8][4];
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mma_compute_scores<Traits>(Qa, bK, lane, Sacc);
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#pragma unroll
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for (int n8 = 0; n8 < Traits::NC8; n8++)
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Sacc[n8][0] *= p.scale, Sacc[n8][1] *= p.scale,
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Sacc[n8][2] *= p.scale, Sacc[n8][3] *= p.scale;
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// Decode: q_len=1, so qrow0=qrow1=0. Paged treats [0, seq_len) as
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// the causal range (query is the last token); contig clips to the
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// causal_offset bound. Dead code eliminated when IsCausal == false.
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int maxc = IsCausal ? KV::decode_attend_len(p, batch) : seq_len;
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mma_softmax_tile<Traits, HasMask>(kv0, maxc, maxc,
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0, 0,
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p.mask_b_stride, p.mask_h_stride, p.mask_l_stride,
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batch, q_head0 + gid, q_head0 + gid + 8,
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p.mask,
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va, vb,
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Sacc, Oacc, m0, m1, l0, l1, lane);
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mma_pv_accumulate<Traits>(Sacc, bV, lane, Oacc);
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};
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if (ntiles >= STAGES) {
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#pragma unroll
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for (int i = 0; i < STAGES; i++)
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load_tile(ti_begin + i, i);
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for (int it = 0; it < ntiles; it++) {
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if (it + 1 == ntiles)
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cp_async_wait_group<0>();
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else
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cp_async_wait_group<STAGES - 1>();
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__syncwarp();
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process_tile(it, it & (STAGES - 1));
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__syncwarp();
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if (it + STAGES < ntiles)
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load_tile(ti_begin + it + STAGES, (it + STAGES) & (STAGES - 1));
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}
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} else {
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// Fewer tiles than stages: load all, wait for all, process.
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for (int i = 0; i < ntiles; i++)
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load_tile(ti_begin + i, i);
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cp_async_wait_group<0>();
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__syncwarp();
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for (int it = 0; it < ntiles; it++)
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process_tile(it, it);
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}
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// ---- write UN-normalised partials for this split ----
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auto split_slot = [&](int h) -> size_t {
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size_t bh = (size_t)batch * p.q_head + h;
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return bh * MAX_SPLITS + split;
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};
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#pragma unroll
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for (int dn8 = 0; dn8 < Traits::DN8; dn8++) {
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int d = dn8 * 8 + 2 * tid4;
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int r0 = gid, r1 = gid + 8;
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if (r0 < G) {
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int h = q_head0 + r0;
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float* op = p.o_part + split_slot(h) * Traits::HEAD_DIM;
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op[d] = Oacc[dn8][0];
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op[d + 1] = Oacc[dn8][1];
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}
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if (r1 < G) {
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int h = q_head0 + r1;
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float* op = p.o_part + split_slot(h) * Traits::HEAD_DIM;
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op[d] = Oacc[dn8][2];
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op[d + 1] = Oacc[dn8][3];
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}
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}
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if (tid4 == 0) {
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int r0 = gid, r1 = gid + 8;
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if (r0 < G) {
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int h = q_head0 + r0;
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float* mp = p.ml_part + split_slot(h) * 2;
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mp[0] = m0; mp[1] = l0;
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}
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if (r1 < G) {
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int h = q_head0 + r1;
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float* mp = p.ml_part + split_slot(h) * 2;
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mp[0] = m1; mp[1] = l1;
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}
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}
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}
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