ViperEkura
aa08479285
- 128x128 CTA of 8 warps x 64x32 warp tiles: 16 mma.sync per warp per K-segment (was 8) - ldmatrix.x4/x2 with per-lane swizzled addresses replaces 36 scalar LDS per warp-tile step - __launch_bounds__(256, 2) caps registers at 124 so two CTAs fit per SM - fp8 linear vs bf16 cuBLAS: fwd 1.07x->2.65x, bwd 1.41x->2.65x by size, peak 31-33 TFLOPS
503 lines
23 KiB
Plaintext
503 lines
23 KiB
Plaintext
#pragma once
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// FP8 GEMM device code — pure CUDA, no torch. Mirrors the attention kernel
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// layout (attn_*_mma.cuh): kernels take the FP8Params POD, tile shape and
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// FP8 format ride on compile-time template parameters, and launchers are
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// plain functions usable from both the torch binding and pure C tests.
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#include <cuda_bf16.h>
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#include <cuda_fp8.h>
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#include <cuda_runtime.h>
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#include <type_traits>
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#include "common.h"
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#include "../common/mma.cuh"
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namespace fp8 {
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// m16n8k32 (see astrai::mma_shape<fp8 type>::k in common/mma.cuh)
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constexpr int kMmaK = 32;
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constexpr int kWarps = 8; // 128x128 CTA = 8 warps
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// Map the FP8Format enum to the CUDA fp8 element type consumed by mma_sync.
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template <FP8Format Fmt>
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struct fp8_input {
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using type = __nv_fp8_e4m3;
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};
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template <>
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struct fp8_input<FP8Format::E5M2> {
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using type = __nv_fp8_e5m2;
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};
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// ---------------------------------------------------------------------------
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// Shared device helpers
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// ---------------------------------------------------------------------------
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// FP8 MMA lives in the shared astrai::mma_sync template (common/mma.cuh);
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// instantiate it with fp8_input<Fmt>::type. Accumulates in-place: callers
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// pass the same accumulator array as both `d` and `c`.
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__device__ __forceinline__ void atomic_max_float(float* destination,
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float value) {
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if (destination)
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atomicMax(reinterpret_cast<unsigned*>(destination),
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__float_as_uint(value));
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}
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__device__ __forceinline__ float warp_reduce_max(float value) {
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#pragma unroll
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for (int offset = 16; offset; offset >>= 1) {
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value = fmaxf(value, __shfl_xor_sync(0xffffffffu, value, offset));
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}
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return value;
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}
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// One thread moves sixteen FP8 values (16 bytes) via cp.async.
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template <typename T>
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__device__ __forceinline__ void cp_async_16b(T* destination,
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const T* source, bool valid) {
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const unsigned shared_address = __cvta_generic_to_shared(destination);
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const uint4* source_vec = reinterpret_cast<const uint4*>(source);
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asm volatile("cp.async.cg.shared.global [%0], [%1], 16, %2;"
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:: "r"(shared_address), "l"(source_vec),
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"r"(valid ? 16 : 0));
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}
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// PTX requires wait_group's operand to be an immediate value. Keep it as a
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// template argument so the stage policy remains compile-time configurable.
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template <int KeepGroups>
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__device__ __forceinline__ void cp_async_wait_group() {
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static_assert(KeepGroups >= 0 && KeepGroups <= 7,
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"cp.async.wait_group supports immediates in [0, 7]");
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asm volatile("cp.async.wait_group %0;" :: "n"(KeepGroups));
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}
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template <int MaxKeepGroups>
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__device__ __forceinline__ void cp_async_wait_group_dispatch(int keep_groups) {
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static_assert(MaxKeepGroups >= 0 && MaxKeepGroups <= 7,
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"cp.async.wait_group supports immediates in [0, 7]");
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if (keep_groups == MaxKeepGroups) {
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cp_async_wait_group<MaxKeepGroups>();
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} else if constexpr (MaxKeepGroups > 0) {
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cp_async_wait_group_dispatch<MaxKeepGroups - 1>(keep_groups);
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} else {
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cp_async_wait_group<0>();
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}
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}
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template <int Stages>
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__device__ __forceinline__ void cp_async_commit_group() {
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static_assert(Stages >= 1 && Stages <= 8,
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"FP8 GEMM stages must be in the range [1, 8]");
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asm volatile("cp.async.commit_group;");
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}
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// ---------------------------------------------------------------------------
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// Quantize kernel: BF16 -> FP8 (E4M3 or E5M2), fused amax over raw values.
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// ---------------------------------------------------------------------------
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// Convert one packed bf16 pair to one packed fp8 pair. amax sees the *raw*
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// (unscaled) values; the stored bytes see value * inv. Bit-identical to the
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// scalar __nv_fp8_*(q) constructor path (round-nearest-even + satfinite).
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template <FP8Format Fmt>
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__device__ __forceinline__ unsigned quantize2(unsigned pair, float inv,
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float& amax) {
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const float lo = __bfloat162float(__ushort_as_bfloat16(pair & 0xffffu));
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const float hi = __bfloat162float(__ushort_as_bfloat16(pair >> 16));
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amax = fmaxf(amax, fmaxf(fabsf(lo), fabsf(hi)));
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constexpr __nv_fp8_interpretation_t kFmt =
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Fmt == FP8Format::E5M2 ? __NV_E5M2 : __NV_E4M3;
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return static_cast<unsigned>(
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__nv_cvt_float2_to_fp8x2(make_float2(lo * inv, hi * inv),
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__NV_SATFINITE, kFmt));
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}
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template <FP8Format Fmt>
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__global__ void fp8_quantize_kernel(FP8Params p) {
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const float inv = 1.0f / *p.scale_a;
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const auto* x = reinterpret_cast<const __nv_bfloat16*>(p.a_ptr);
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void* x8 = p.out_ptr;
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float* amax = p.amax_a;
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float local_amax = 0.0f;
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const int64_t stride = (int64_t)blockDim.x * gridDim.x;
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// Vectorized body: 8 bf16 (16B load) -> 8 fp8 (8B store) per step. Torch
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// allocations are >=16B aligned and the binding passes freshly allocated
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// contiguous buffers, so element 0 keeps the uint4/uint2 accesses
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// natural; a misaligned base (contiguous view with an odd storage
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// offset) falls back to the scalar loop below via total_vec = 0.
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const bool aligned =
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((reinterpret_cast<uintptr_t>(x) | reinterpret_cast<uintptr_t>(x8))
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& 15) == 0;
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const int64_t total_vec = aligned ? p.total / 8 : 0;
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const uint4* xv = reinterpret_cast<const uint4*>(x);
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uint2* o8 = reinterpret_cast<uint2*>(x8);
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for (int64_t i = blockIdx.x * blockDim.x + threadIdx.x; i < total_vec;
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i += stride) {
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const uint4 v = xv[i];
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const unsigned pair[4] = {v.x, v.y, v.z, v.w};
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unsigned packed[2] = {0u, 0u};
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#pragma unroll
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for (int j = 0; j < 4; ++j)
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packed[j >> 1] |= quantize2<Fmt>(pair[j], inv, local_amax)
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<< (16 * (j & 1));
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o8[i] = make_uint2(packed[0], packed[1]);
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}
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// Scalar tail (and full fallback for misaligned bases).
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for (int64_t i = total_vec * 8 + blockIdx.x * blockDim.x + threadIdx.x;
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i < p.total; i += stride) {
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const float f = __bfloat162float(x[i]);
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local_amax = fmaxf(local_amax, fabsf(f));
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if constexpr (Fmt == FP8Format::E5M2) {
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reinterpret_cast<__nv_fp8_e5m2*>(x8)[i] = __nv_fp8_e5m2(f * inv);
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} else {
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reinterpret_cast<__nv_fp8_e4m3*>(x8)[i] = __nv_fp8_e4m3(f * inv);
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}
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}
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if (amax) {
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local_amax = warp_reduce_max(local_amax);
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__shared__ float slots[32];
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if ((threadIdx.x & 31) == 0) slots[threadIdx.x >> 5] = local_amax;
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__syncthreads();
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if (threadIdx.x == 0) {
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float v = 0.0f;
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for (int w = 0; w < (blockDim.x >> 5); ++w) v = fmaxf(v, slots[w]);
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atomic_max_float(amax, v);
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}
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}
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}
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// Swizzled address inside a flat [rows * K] staging tile: the 16-byte chunk
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// index is XORed with row bits starting at bit 2. Unswizzled, a kK=32 row
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// spans only 8 words, so a warp's fragment load (8 consecutive rows x 4B,
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// e.g. a_row0+0..7) maps rows r and r+4 onto the same banks — a 2-way
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// conflict on every LDS. XORing the chunk index with row bit 2 shifts rows
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// 4..7 by one chunk so each warp's 32-word read hits all 32 banks exactly
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// once. Chunks stay contiguous, so the cp.async 16B staging path is
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// unaffected. Validated for kK=32 (2 chunks); larger power-of-two chunk
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// counts compile but need their own bank analysis.
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template <int K, typename T8>
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__device__ __forceinline__ T8* tile_at(T8* tile, int row, int col) {
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constexpr int kChunks = K / 16; // 16B chunks per row
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static_assert(kChunks >= 1 && (kChunks & (kChunks - 1)) == 0,
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"swizzle needs a power-of-two 16B-chunk count");
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return tile + row * K
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+ ((((col >> 4) ^ ((row >> 2) & (kChunks - 1))) << 4)
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+ (col & 15));
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}
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// Stage-load one GEMM operand into the canonical flat [rows * K] shared tile
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// (addressing via tile_at, so stores land in the swizzled layout). The
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// transpose is folded into the staging step via a CUTLASS-style crosswise
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// layout: the congruous case copies 16-byte K-contiguous runs with cp.async,
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// while the transposed case reads 16-byte runs along the operand's contiguous
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// (non-contract) dim and scatters them across the tile's rows. `block_row` is
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// this block's origin in the operand's row dim; the caller restricts which
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// threads invoke it (all threads for A, the first 128 for B).
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template <typename T8, int K, bool Trans>
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__device__ __forceinline__ void load_operand_tile(
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T8* tile, const T8* __restrict__ operand, int64_t rows,
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int64_t contract, int64_t ld, int tid, int64_t k_base,
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int64_t block_row) {
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if constexpr (Trans) {
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// Operand stored [contract][rows]: contiguous along the non-contract dim.
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const int rg = tid >> 5; // Rows / 16 row-groups
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const int kl = tid & 31; // K lanes
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const int64_t k_idx = k_base + kl;
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const int64_t r0 = block_row + rg * 16;
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const auto* src = operand + k_idx * ld + r0;
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const bool aligned = (reinterpret_cast<uintptr_t>(src) & 15) == 0;
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if (k_idx < contract && r0 + 15 < rows && aligned) {
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const uint4 v = *reinterpret_cast<const uint4*>(src);
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const auto* bytes = reinterpret_cast<const T8*>(&v);
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// Scatter 16 bytes along the tile rows. The swizzle bit flips
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// every 4 rows ((rg*16 + i) >> 2 & 1 == (i >> 2) & 1), and the
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// physical column of row group g is kl ^ (16 * (g & 1)) — so the
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// whole 16-byte scatter is one base pointer plus two alternating
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// column offsets, no per-byte XOR in the address math.
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#pragma unroll
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for (int g = 0; g < 4; ++g) {
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T8* p = tile + (rg * 16 + 4 * g) * K
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+ (g & 1 ? (kl ^ 16) : kl);
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p[0] = bytes[4 * g];
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p[K] = bytes[4 * g + 1];
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p[2 * K] = bytes[4 * g + 2];
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p[3 * K] = bytes[4 * g + 3];
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}
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} else {
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// Predicated fallback: same layout, byte-granular gather.
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const int col = kl;
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#pragma unroll
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for (int g = 0; g < 4; ++g) {
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const T8* src_g = operand + k_idx * ld + r0 + 4 * g;
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T8* p = tile + (rg * 16 + 4 * g) * K
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+ (g & 1 ? (col ^ 16) : col);
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#pragma unroll
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for (int i = 0; i < 4; ++i) {
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const int64_t r_idx = r0 + 4 * g + i;
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p[i * K] = (r_idx < rows && k_idx < contract)
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? src_g[i]
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: T8(0.0f);
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}
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}
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}
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} else {
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// Operand stored [rows][contract]: contiguous along the contract dim.
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const int r = tid >> 1;
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const int c = (tid & 1) * 16;
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const int64_t row = block_row + r;
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// c is a multiple of 16, so the whole 16-byte run shares one chunk
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// and dst[i] addressing below matches tile_at<K>(tile, r, c + i).
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T8* dst = tile_at<K>(tile, r, c);
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const auto* src = operand + row * ld + k_base + c;
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const bool full = k_base + c + 15 < contract;
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if (row < rows && full &&
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(reinterpret_cast<uintptr_t>(src) & 15) == 0) {
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cp_async_16b(dst, src, true);
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} else {
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#pragma unroll
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for (int i = 0; i < 16; ++i)
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dst[i] = row < rows && k_base + c + i < contract ? src[i]
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: T8(0.0f);
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}
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}
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}
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// ---------------------------------------------------------------------------
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// Pre-quantized GEMM kernel: FP8 A/B read straight into shared memory, FP32
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// accumulation, BF16 or FP8 output. The input format follows Traits; the
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// tile is compact (row = kK bytes) so MMA fragments read directly — no
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// in-kernel transpose of the operands (the binding handles transposes).
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// ---------------------------------------------------------------------------
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// ldmatrix with per-lane addresses (unlike common/mma.cuh's single-address
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// helpers, the fragment tiles here are XOR-swizzled per 16B chunk, so each
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// lane computes its own row/chunk address). Layout contract for fp8
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// m16n8k32 (values packed two-per-b16 slot, K-contiguous rows):
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// x4 (A fragment): lane i points at tile row (i>>3 & 1)*8 + (i&7) of
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// chunk (k_seg*2 + (i>>4)); reg j = matrix j = [row g][tig*4..+3] in
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// the order (rows 0-7 c, rows 8-15 c, rows 0-7 c+1, rows 8-15 c+1) —
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// exactly the mma.sync A operand layout.
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// x2 (B fragment): lane i points at tile row (i&7) of chunk
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// (k_seg*2 + ((i>>3) & 1)); reg j = [row(n) g][tig*4..+3] chunk c/c+1
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// — exactly the mma.sync B operand layout (col operand, K-contiguous).
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__device__ __forceinline__ void ldsm_x2(unsigned r[2], unsigned addr) {
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asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0,%1}, [%2];"
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: "=r"(r[0]), "=r"(r[1])
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: "r"(addr));
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}
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__device__ __forceinline__ void ldsm_x4(unsigned r[4], unsigned addr) {
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asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0,%1,%2,%3}, [%4];"
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: "=r"(r[0]), "=r"(r[1]), "=r"(r[2]), "=r"(r[3])
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: "r"(addr));
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}
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// Swizzled 16B-chunk address (tile_at's layout) as a raw shared-memory
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// pointer for ldmatrix. Requires kK == 32 (2 chunks/row swizzle).
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template <typename T8, int kK>
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__device__ __forceinline__ unsigned frag_addr(const T8* tile, int row,
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int chunk) {
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static_assert(kK == 32, "fragment swizzle offsets assume kK == 32");
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return __cvta_generic_to_shared(
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tile + row * kK + (((chunk ^ ((row >> 2) & 1)) << 4)));
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}
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// TransA / TransB select the operand memory layout. The kernel always computes
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// out[m][n] = sum_p tileA[m][p] * tileB[n][p]
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// with the tiles materialized in the canonical [M][kK] / [N][kK] layout, so the
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// MMA fragments are read identically regardless of layout. The two flags only
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// change how the stage-load gathers the operand from global memory:
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// TransA: tileA[m][p] = a[p*a_ld + m] (A stored [K][M], i.e. A^T)
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// else a[m*a_ld + p] (A stored [M][K])
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// TransB: tileB[n][p] = b[n*b_ld + p] (B stored [N][K])
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// else b[p*b_ld + n] (B stored [K][N], read transposed)
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template <typename Traits, bool OutFp8 = false, bool TransA = false,
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bool TransB = false>
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__global__ void __launch_bounds__(kWarps * 32, 2) fp8_gemm_kernel(FP8Params p) {
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using T8 = std::conditional_t<Traits::kIsE5M2, __nv_fp8_e5m2, __nv_fp8_e4m3>;
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constexpr int kBlockM = Traits::kBlockM;
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constexpr int kBlockN = Traits::kBlockN;
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constexpr int kK = Traits::kK;
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constexpr int kStages = Traits::kStages;
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static_assert(kStages >= 1 && kStages <= 8,
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"FP8 GEMM stages must be in the range [1, 8]");
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// Tiles are flat [rows * kK] with a 16B-chunk XOR swizzle (tile_at):
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// ldmatrix reads whole 16B chunks through the same mapping the staging
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// writes, and the swizzle removes the bank conflict the unswizzled
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// 8-word row stride caused (see tile_at).
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__shared__ __align__(16) T8 a_smem[kStages][kBlockM * kK];
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__shared__ __align__(16) T8 b_smem[kStages][kBlockN * kK];
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const auto* a = reinterpret_cast<const T8*>(p.a_ptr);
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const auto* b = reinterpret_cast<const T8*>(p.b_ptr);
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auto* out_bf16 = reinterpret_cast<__nv_bfloat16*>(p.out_ptr);
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auto* out_fp8 = reinterpret_cast<__nv_fp8_e4m3*>(p.out_ptr);
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const int64_t m = p.m, n = p.n, k = p.k;
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const int64_t a_ld = p.a_ld, b_ld = p.b_ld;
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const int tid = threadIdx.x;
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const int warp = tid >> 5;
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const int lane = tid & 31;
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const int group = lane >> 2;
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const int thread_in_group = lane & 3;
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// 128x128 CTA = 8 warps as 2x4 warp tiles of 64x32 (mt x nt = 4x4 MMA).
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constexpr int warps_n = kBlockN / 32;
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const int warp_m = warp / warps_n;
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const int warp_n = warp % warps_n;
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const int64_t row_base = blockIdx.y * kBlockM + warp_m * 64 + group;
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const int64_t output_col =
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blockIdx.x * kBlockN + warp_n * 32 + thread_in_group * 2;
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const int a_row0 = warp_m * 64; // + mt * 16 in the loop
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const int b_row0 = warp_n * 32; // + nt * 8
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const float sa = *p.scale_a;
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const float sb = *p.scale_b;
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float acc[4][4][4] = {}; // [nt][mt][acc]
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// Both operands are staged into the canonical [M][kK] / [N][kK] shared
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// tiles regardless of their global layout (see load_operand_tile), so the
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// MMA fragment reads below stay unchanged across the four layout flags.
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// Each 128x32 tile is 256 16B chunks: one per thread.
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auto load_tile = [&](int stage, int64_t k_base) {
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// load_operand_tile's `Trans` means "the operand's contiguous dim is
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// the non-contract dim" (crosswise load). For A that is TransA; for B
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// the storage flag is inverted (TransB=true stores B as [N][K], i.e.
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// K-contiguous, which is the congruous case).
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load_operand_tile<T8, kK, TransA>(
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a_smem[stage], a, m, k, a_ld, tid, k_base, blockIdx.y * kBlockM);
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load_operand_tile<T8, kK, !TransB>(
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b_smem[stage], b, n, k, b_ld, tid, k_base, blockIdx.x * kBlockN);
|
|
};
|
|
|
|
const int64_t tile_count = (k + kK - 1) / kK;
|
|
|
|
// Per-lane ldmatrix row/chunk selectors (see ldsm_x2/ldsm_x4 contract).
|
|
const int r7 = lane & 7; // row within the 8-row matrix
|
|
const int rh8 = (lane >> 3) & 1; // +8 rows (A: lanes 8-15, 24-31)
|
|
const int rh16 = lane >> 4; // +1 chunk (A: lanes 16-31; B uses rh8)
|
|
|
|
// Prime the pipeline. Each committed group occupies one circular shared
|
|
// memory stage; the loop also handles K dimensions smaller than kStages.
|
|
#pragma unroll
|
|
for (int stage = 0; stage < kStages; ++stage) {
|
|
if (stage < tile_count) {
|
|
load_tile(stage, static_cast<int64_t>(stage) * kK);
|
|
cp_async_commit_group<kStages>();
|
|
}
|
|
}
|
|
|
|
for (int64_t tile_index = 0; tile_index < tile_count; ++tile_index) {
|
|
const int stage = static_cast<int>(tile_index % kStages);
|
|
const int64_t remaining = tile_count - tile_index - 1;
|
|
|
|
// Keep up to kStages - 1 younger groups in flight while making the
|
|
// oldest group (the current stage) ready for consumption.
|
|
const int keep_groups =
|
|
remaining < kStages - 1 ? static_cast<int>(remaining) : kStages - 1;
|
|
cp_async_wait_group_dispatch<kStages - 1>(keep_groups);
|
|
// Barrier 1: every thread's cp.async for this stage is complete
|
|
// before any thread reads tiles written by other threads.
|
|
__syncthreads();
|
|
|
|
// 4 ldmatrix.x2 (B) + 4 ldmatrix.x4 (A) feed 16 mma.sync per k_seg —
|
|
// 0.5 load instructions per MMA, versus 4.5 scalar LDS per MMA in
|
|
// the 128x64-tile version (the kernel was LSU-issue-bound there).
|
|
#pragma unroll
|
|
for (int k_seg = 0; k_seg < kK / kMmaK; ++k_seg) {
|
|
unsigned b_frag[4][2];
|
|
#pragma unroll
|
|
for (int nt = 0; nt < 4; ++nt) {
|
|
const int row = b_row0 + nt * 8 + r7;
|
|
ldsm_x2(b_frag[nt],
|
|
frag_addr<T8, kK>(b_smem[stage], row,
|
|
k_seg * 2 + rh8));
|
|
}
|
|
#pragma unroll
|
|
for (int mt = 0; mt < 4; ++mt) {
|
|
unsigned a_frag[4];
|
|
const int row = a_row0 + mt * 16 + rh8 * 8 + r7;
|
|
ldsm_x4(a_frag,
|
|
frag_addr<T8, kK>(a_smem[stage], row,
|
|
k_seg * 2 + rh16));
|
|
#pragma unroll
|
|
for (int nt = 0; nt < 4; ++nt)
|
|
astrai::mma_sync<T8>(acc[nt][mt], a_frag, b_frag[nt],
|
|
acc[nt][mt]);
|
|
}
|
|
}
|
|
// Barrier 2: every thread finished reading this stage's tiles before
|
|
// the prefetch for the (i+kStages)-th tile overwrites them.
|
|
__syncthreads();
|
|
if (tile_index + kStages < tile_count) {
|
|
load_tile(stage, (tile_index + kStages) * kK);
|
|
cp_async_commit_group<kStages>();
|
|
}
|
|
}
|
|
|
|
const float output_scale = sa * sb;
|
|
const float o8_scale = OutFp8 ? output_scale * *p.out_scale : 0.0f;
|
|
#pragma unroll
|
|
for (int nt = 0; nt < 4; ++nt) {
|
|
const int64_t col = output_col + nt * 8;
|
|
// Per-row store: FP8 packs two adjacent columns into one 16-bit
|
|
// write; the BF16 path writes two scalars. Boundary columns fall
|
|
// back to a scalar convert so the pack never crosses the row edge.
|
|
auto store_out = [&](int64_t row, float v0, float v1) {
|
|
if (row >= m) return;
|
|
if constexpr (OutFp8) {
|
|
if (col + 1 < n) {
|
|
*reinterpret_cast<unsigned short*>(out_fp8 + row * n + col) =
|
|
static_cast<unsigned short>(__nv_cvt_float2_to_fp8x2(
|
|
make_float2(v0 * o8_scale, v1 * o8_scale),
|
|
__NV_SATFINITE, __NV_E4M3));
|
|
} else {
|
|
out_fp8[row * n + col] = __nv_fp8_e4m3(v0 * o8_scale);
|
|
}
|
|
} else {
|
|
out_bf16[row * n + col] = __float2bfloat16(v0 * output_scale);
|
|
if (col + 1 < n)
|
|
out_bf16[row * n + col + 1] =
|
|
__float2bfloat16(v1 * output_scale);
|
|
}
|
|
};
|
|
#pragma unroll
|
|
for (int mt = 0; mt < 4; ++mt) {
|
|
const int64_t row0 = row_base + mt * 16;
|
|
float* tile_acc = acc[nt][mt];
|
|
if (col < n) {
|
|
store_out(row0, tile_acc[0], tile_acc[1]);
|
|
store_out(row0 + 8, tile_acc[2], tile_acc[3]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// ---------------------------------------------------------------------------
|
|
// Launchers — pure CUDA (no torch), usable from the binding and pure C tests.
|
|
// ---------------------------------------------------------------------------
|
|
|
|
template <FP8Format Fmt>
|
|
void launch_fp8_quantize(const FP8Params& p, cudaStream_t stream) {
|
|
constexpr int kThreads = 256;
|
|
// One block per 256 vectors (8 elements each); at least one block so the
|
|
// scalar tail of a tiny / misaligned tensor is still covered.
|
|
int64_t blocks = (p.total / 8 + kThreads - 1) / kThreads;
|
|
if (blocks < 1) blocks = 1;
|
|
fp8_quantize_kernel<Fmt><<<blocks, kThreads, 0, stream>>>(p);
|
|
}
|
|
|
|
// Pre-quantized GEMM tile config: 128x128 CTA (8 warps x 64x32 warp tiles),
|
|
// K=32, 3-stage pipeline (24KB smem -> 2 CTAs/SM). The wide warp tile plus
|
|
// ldmatrix fragments lifts the LSU-issue bound of the old 128x64 config.
|
|
// Stages remains an explicit template override for tuning. TransA/TransB
|
|
// mirror the kernel template (defaults keep the NN layout: out = a @ b).
|
|
template <FP8Format Fmt, bool OutFp8 = false, bool TransA = false,
|
|
bool TransB = false, int Stages = 3>
|
|
void launch_fp8_gemm(const FP8Params& p, cudaStream_t stream) {
|
|
using Traits = Fp8GemmTraits<Fmt, 128, 128, 32, Stages>;
|
|
dim3 grid((p.n + Traits::kBlockN - 1) / Traits::kBlockN,
|
|
(p.m + Traits::kBlockM - 1) / Traits::kBlockM);
|
|
fp8_gemm_kernel<Traits, OutFp8, TransA, TransB><<<grid, kWarps * 32, 0, stream>>>(p);
|
|
}
|
|
|
|
} // namespace fp8
|