197 lines
9.0 KiB
Plaintext
197 lines
9.0 KiB
Plaintext
#pragma once
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#include <cfloat>
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#include <cuda_bf16.h>
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#include "attn_common.h"
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#include "attn_mma_utils.cuh"
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using bf16 = __nv_bfloat16;
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// Tensor-core prefill flash attention (raw mma.sync PTX).
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// One warp owns BR=16 query rows. S = Q@K^T and O = P@V run on bf16 tensor
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// cores via mma.sync.m16n8k16 (f32 accumulate). Q fragments are loaded once
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// straight from global into the mma A-operand layout (no smem staging) and
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// kept resident in registers across the tile loop. S, O, and the online-softmax
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// stats (m, l) also live in registers.
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// Shared memory is statically sized via template parameters — no dynamic
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// allocation. The mma fragment layout is used directly: the S accumulator
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// (f32) maps element-for-element onto the P matrix_a (bf16) operand, so
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// softmax needs no shuffle repack; row reductions fold across the 4-lane
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// thread group. Templated on <HEAD_DIM, WARPS, BC> with BC a multiple of 16.
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//
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// Software pipeline: K/V are double-buffered and loaded via cp.async one tile
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// ahead, so the next tile streams from global memory while the current tile's
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// tensor-core math runs — hiding load latency (long_scoreboard). A single
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// __syncthreads per tile both publishes the freshly loaded tile cross-warp and
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// (because it runs before the next prefetch) guards the buffer being refilled,
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// so no second barrier is needed. Predicated cp.async (cp_async_16_pred)
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// zero-fills rows past kv_len, unifying full and partial tiles on one path.
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// BC=32 (D<=128) amortizes the per-tile wait+barrier+loop overhead over more
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// tensor-core work — this kernel is latency-bound (low occupancy from high
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// register pressure), so fewer, larger tiles beat many tiny ones.
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//
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// Optimizations: load Q fragments directly from global in mma A-operand layout
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// (no sQ staging, no prologue barriers); post-multiply scale in float after
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// S=Q@K^T to avoid bf16 precision loss; packed bf16x2 output stores;
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// causal tile skipping (block-level prefetch bound + warp-level compute skip);
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// XOR swizzle (swiz_col) → eliminates ldmatrix bank conflicts without LD
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// padding (LD=HEAD_DIM).
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template <int HEAD_DIM, int WARPS, int BC>
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__global__ void attn_prefill_split_q_mma_kernel(AttentionParams<bf16> p) {
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constexpr int BR = 16;
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constexpr int KD = HEAD_DIM / 16; // Q/K k-tiles
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constexpr int NC8 = BC / 8; // S n-tiles (N=8 each)
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constexpr int KT2 = BC / 16; // P k-tiles (K=16 each)
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constexpr int DN8 = HEAD_DIM / 8; // O n-tiles (N=8 each)
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constexpr int LD = HEAD_DIM; // XOR swizzle (swiz_col) handles bank conflicts
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constexpr int SWIZ_MASK = (HEAD_DIM >= 64) ? 7 : (HEAD_DIM / 8 - 1); // chunk bits, stay within LD
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const int warp = threadIdx.x / 32;
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const int lane = threadIdx.x % 32;
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const int gid = lane >> 2; // 0..7 → rows gid, gid+8
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const int tid4 = lane & 3; // 0..3
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const int nthreads = WARPS * 32;
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const int q_head = blockIdx.y;
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const int batch = blockIdx.z;
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const int kv_head = q_head / (p.q_head / p.kv_head);
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const int qrow0 = (blockIdx.x * WARPS + warp) * BR;
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// ---- Static shared memory: double-buffered K/V ----
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// K/V are double-buffered (STAGES=2): the next tile's cp.async load runs
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// while the current tile's tensor-core math executes, hiding global-load
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// latency (FA2-style software pipeline). No dynamic smem / carveout opt-in.
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constexpr int STAGES = 2;
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__shared__ __align__(16) bf16 sK[STAGES * BC * LD];
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__shared__ __align__(16) bf16 sV[STAGES * BC * LD];
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// Load Q fragments straight from global into mma A-operand layout.
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// stride_row = p.q_stride_l for prefill (multi-q rows across q_len).
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// See attn_mma_utils.cuh for the shared template.
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const int q_base = batch * p.q_stride_b + q_head * p.q_stride_h;
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const int qra = qrow0 + gid;
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const int qrb = qrow0 + gid + 8;
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const bool va = qra < p.q_len, vb = qrb < p.q_len;
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unsigned Qa[KD][4];
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load_q_mma_frags<KD>(p.q + q_base, p.q_stride_l, p.q_stride_d,
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qra, qrb, va, vb, tid4, Qa);
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float Oacc[DN8][4];
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#pragma unroll
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for (int j = 0; j < DN8; j++)
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Oacc[j][0] = Oacc[j][1] = Oacc[j][2] = Oacc[j][3] = 0.0f;
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float m0 = -FLT_MAX, m1 = -FLT_MAX, l0 = 0.0f, l1 = 0.0f;
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// KV: stride-based base
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const int kv_base = batch * p.kv_stride_b + kv_head * p.kv_stride_h;
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const int tiles = (p.kv_len + BC - 1) / BC;
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const int qr0 = qrow0 + gid; // row for c0/c1
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const int qr1 = qrow0 + gid + 8; // row for c2/c3
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// Causal tile-skip bounds (no-op when causal_offset < 0)
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const int use_skip = (p.causal_offset >= 0) ? 1 : 0;
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const int max_kv = qrow0 + BR - 1 + p.causal_offset;
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const int block_max_kv =
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blockIdx.x * WARPS * BR + WARPS * BR - 1 + p.causal_offset;
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const int has_mask = p.use_mask && p.mask;
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// Last active tile: block-level causal bound (all warps in the block share
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// the K/V load, so the prefetch range is the block max, not per-warp).
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int t_end = tiles - 1;
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if (use_skip) {
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int bt = block_max_kv / BC;
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if (bt < t_end) t_end = bt;
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}
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constexpr int VEC = 8; // bf16 per cp.async unit (16 bytes)
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constexpr int TOTAL = BC * HEAD_DIM;
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// ---- Load tile lambda: predicated cp.async ----
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// Issue cp.async loads for tile `ti` into shared buffer `buf`. Predicated
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// loads zero-fill rows past kv_len, so partial tiles need no scalar path.
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auto load_tile = [&](int ti, int buf) {
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int kv0 = ti * BC;
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bf16* dK = sK + buf * BC * LD;
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bf16* dV = sV + buf * BC * LD;
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#pragma unroll
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for (int i = threadIdx.x * VEC; i < TOTAL; i += nthreads * VEC) {
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int r = i / HEAD_DIM, d = i % HEAD_DIM;
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int kc = kv0 + r;
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bool valid = kc < p.kv_len;
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int off = r * LD + swiz_col(d, r, SWIZ_MASK);
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int g_off = kv_base + kc * p.kv_stride_l + d * p.kv_stride_d;
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cp_async_16_pred(&dK[off], &p.k[g_off], valid);
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cp_async_16_pred(&dV[off], &p.v[g_off], valid);
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}
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cp_async_commit();
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};
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// ---- Prologue: issue first tile load ----
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load_tile(0, 0);
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for (int ti = 0; ti <= t_end; ti++) {
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int buf = ti & 1;
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// Wait for the current tile's async copies, then a single barrier: it
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// both publishes this tile's data cross-warp AND guarantees the prior
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// compute on the buffer we are about to refill has finished. Issuing
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// the next tile's load *after* this barrier lets one barrier cover both
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// hazards (vs two), while the load still overlaps this tile's math.
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cp_async_wait_group<0>();
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__syncthreads();
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if (ti < t_end) load_tile(ti + 1, (ti + 1) & 1);
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const bf16* bK = sK + buf * BC * LD;
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const bf16* bV = sV + buf * BC * LD;
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int kv0 = ti * BC;
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// Warp-level causal skip
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if (!use_skip || kv0 <= max_kv) {
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// S = Q @ K^T + scale + online softmax + O += P @ V
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float Sacc[NC8][4];
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mma_compute_scores<KD, NC8>(Qa, bK, LD, SWIZ_MASK, lane, Sacc);
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// post-multiply scale in float (no bf16 precision loss from pre-scaling Q)
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#pragma unroll
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for (int n8 = 0; n8 < NC8; n8++)
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Sacc[n8][0] *= p.scale, Sacc[n8][1] *= p.scale,
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Sacc[n8][2] *= p.scale, Sacc[n8][3] *= p.scale;
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int maxc0 = (p.causal_offset >= 0) ? min(p.kv_len, qr0 + p.causal_offset + 1)
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: p.kv_len;
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int maxc1 = (p.causal_offset >= 0) ? min(p.kv_len, qr1 + p.causal_offset + 1)
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: p.kv_len;
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mma_softmax_tile<NC8, DN8>(kv0, maxc0, maxc1,
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qr0, qr1,
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p.mask_b_stride, p.mask_q_stride,
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batch,
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p.mask, has_mask,
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Sacc, Oacc, m0, m1, l0, l1, lane);
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mma_pv_accumulate<DN8, KT2>(Sacc, bV, LD, SWIZ_MASK, lane, Oacc);
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} // if active (warp-level causal skip)
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}
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// ---- write output ---- (packed bf16x2 stores: one 32-bit STG per pair,
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// halves store count and removes the uncoalesced scalar-store penalty)
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float rl0 = (l0 > 1e-20f) ? (1.0f / l0) : 0.0f;
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float rl1 = (l1 > 1e-20f) ? (1.0f / l1) : 0.0f;
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// O: stride-based write
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const int o_base = batch * p.q_stride_b + q_head * p.q_stride_h;
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#pragma unroll
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for (int dn8 = 0; dn8 < DN8; dn8++) {
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int d = dn8 * 8 + 2 * tid4;
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if (qr0 < p.q_len) {
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__nv_bfloat162 v = __floats2bfloat162_rn(Oacc[dn8][0] * rl0,
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Oacc[dn8][1] * rl0);
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*reinterpret_cast<__nv_bfloat162*>(&p.o[o_base + qr0 * p.q_stride_l + d * p.q_stride_d]) = v;
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}
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if (qr1 < p.q_len) {
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__nv_bfloat162 v = __floats2bfloat162_rn(Oacc[dn8][2] * rl1,
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Oacc[dn8][3] * rl1);
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*reinterpret_cast<__nv_bfloat162*>(&p.o[o_base + qr1 * p.q_stride_l + d * p.q_stride_d]) = v;
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}
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}
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}
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