- add decode-shape benchmark harness - add bf16 GEMV CUDA primitive with head-dim generic kernel - dispatch decode-time linear layers to gemv for M=1 - extend gemv coverage to small decode batches
207 lines
6.7 KiB
Plaintext
207 lines
6.7 KiB
Plaintext
// Directly callable small-M BF16 GEMV primitive for decode-time linear layers.
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#include <ATen/cuda/CUDAContext.h>
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#include <c10/cuda/CUDAGuard.h>
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#include <c10/cuda/CUDAException.h>
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#include <cuda_bf16.h>
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#include <torch/extension.h>
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#include <cstdint>
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#include <limits>
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namespace {
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constexpr int kThreads = 256;
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constexpr int kWarpSize = 32;
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__device__ __forceinline__ float warp_sum(float value) {
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#pragma unroll
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for (int offset = kWarpSize / 2; offset > 0; offset >>= 1) {
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value += __shfl_down_sync(0xffffffff, value, offset);
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}
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return value;
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}
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template <int Rows>
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__global__ void bf16_gemv_kernel(
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const __nv_bfloat16* __restrict__ x,
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const __nv_bfloat16* __restrict__ weight,
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const __nv_bfloat16* __restrict__ bias,
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__nv_bfloat16* __restrict__ output,
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int n,
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int k
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) {
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const int output_index = blockIdx.x;
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const int lane = threadIdx.x & (kWarpSize - 1);
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const int warp = threadIdx.x / kWarpSize;
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const int pairs = k / 2;
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const auto* x2 = reinterpret_cast<const __nv_bfloat162*>(x);
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const auto* w2 =
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reinterpret_cast<const __nv_bfloat162*>(weight) + output_index * pairs;
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float sums[Rows] = {};
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for (int pair = threadIdx.x; pair < pairs; pair += blockDim.x) {
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const __nv_bfloat162 wv = w2[pair];
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#pragma unroll
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for (int row = 0; row < Rows; ++row) {
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const __nv_bfloat162 xv = x2[row * pairs + pair];
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sums[row] = fmaf(
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__bfloat162float(__low2bfloat16(xv)),
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__bfloat162float(__low2bfloat16(wv)),
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sums[row]
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);
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sums[row] = fmaf(
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__bfloat162float(__high2bfloat16(xv)),
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__bfloat162float(__high2bfloat16(wv)),
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sums[row]
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);
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}
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}
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__shared__ float warp_sums[Rows][kThreads / kWarpSize];
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#pragma unroll
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for (int row = 0; row < Rows; ++row) {
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sums[row] = warp_sum(sums[row]);
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}
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if (lane == 0) {
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#pragma unroll
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for (int row = 0; row < Rows; ++row) {
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warp_sums[row][warp] = sums[row];
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}
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}
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__syncthreads();
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if (warp == 0) {
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#pragma unroll
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for (int row = 0; row < Rows; ++row) {
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float sum =
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lane < (kThreads / kWarpSize) ? warp_sums[row][lane] : 0.0f;
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sum = warp_sum(sum);
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if (lane == 0) {
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if (bias != nullptr) {
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sum += __bfloat162float(bias[output_index]);
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}
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output[row * n + output_index] = __float2bfloat16_rn(sum);
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}
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}
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}
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}
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template <int Rows>
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void launch_bf16_gemv(
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const __nv_bfloat16* x,
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const __nv_bfloat16* weight,
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const __nv_bfloat16* bias,
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__nv_bfloat16* output,
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int n,
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int k,
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cudaStream_t stream
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) {
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bf16_gemv_kernel<Rows><<<n, kThreads, 0, stream>>>(
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x, weight, bias, output, n, k
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);
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}
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torch::Tensor bf16_gemv(
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torch::Tensor x,
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torch::Tensor weight,
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py::object bias_object
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) {
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TORCH_CHECK(x.is_cuda() && weight.is_cuda(), "x and weight must be CUDA tensors");
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TORCH_CHECK(x.device() == weight.device(), "x and weight must share device");
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TORCH_CHECK(
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x.scalar_type() == torch::kBFloat16 &&
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weight.scalar_type() == torch::kBFloat16,
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"x and weight must be bf16"
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);
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TORCH_CHECK(
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x.dim() == 1 || x.dim() == 2,
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"x must have shape [K] or [M, K]"
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);
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TORCH_CHECK(weight.dim() == 2, "weight must have shape [N, K]");
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TORCH_CHECK(x.is_contiguous() && weight.is_contiguous(), "x and weight must be contiguous");
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TORCH_CHECK(
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!x.requires_grad() && !weight.requires_grad(),
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"bf16_gemv is inference-only and does not support autograd"
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);
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const int64_t m = x.dim() == 1 ? 1 : x.size(0);
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const int64_t k = x.size(-1);
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const int64_t n = weight.size(0);
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TORCH_CHECK(
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m == 1 || m == 2 || m == 4 || m == 8,
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"M must be one of 1, 2, 4, or 8"
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);
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TORCH_CHECK(weight.size(1) == k, "weight K must match x K");
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TORCH_CHECK(k > 0 && n > 0, "N and K must be positive");
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TORCH_CHECK(k % 2 == 0, "K must be even for vectorized bf16 loads");
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TORCH_CHECK(
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k <= std::numeric_limits<int>::max() &&
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n <= std::numeric_limits<int>::max(),
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"N or K exceeds the CUDA launcher limit"
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);
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torch::Tensor bias;
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const __nv_bfloat16* bias_ptr = nullptr;
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if (!bias_object.is_none()) {
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bias = bias_object.cast<torch::Tensor>();
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TORCH_CHECK(bias.is_cuda() && bias.device() == x.device(), "bias must share the CUDA device");
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TORCH_CHECK(bias.scalar_type() == torch::kBFloat16, "bias must be bf16");
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TORCH_CHECK(bias.dim() == 1 && bias.size(0) == n, "bias must have shape [N]");
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TORCH_CHECK(bias.is_contiguous(), "bias must be contiguous");
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TORCH_CHECK(!bias.requires_grad(), "bf16_gemv bias does not support autograd");
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bias_ptr = reinterpret_cast<const __nv_bfloat16*>(bias.data_ptr());
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}
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const at::cuda::OptionalCUDAGuard guard(x.device());
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const auto* properties = at::cuda::getDeviceProperties(x.device().index());
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TORCH_CHECK(properties->major >= 8, "bf16_gemv requires compute capability 8.0+");
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auto stream = at::cuda::getCurrentCUDAStream();
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auto output = x.dim() == 1 ? torch::empty({n}, x.options())
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: torch::empty({m, n}, x.options());
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const auto* x_ptr = reinterpret_cast<const __nv_bfloat16*>(x.data_ptr());
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const auto* weight_ptr =
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reinterpret_cast<const __nv_bfloat16*>(weight.data_ptr());
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auto* output_ptr = reinterpret_cast<__nv_bfloat16*>(output.data_ptr());
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const int n_int = static_cast<int>(n);
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const int k_int = static_cast<int>(k);
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switch (m) {
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case 1:
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launch_bf16_gemv<1>(
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x_ptr, weight_ptr, bias_ptr, output_ptr, n_int, k_int, stream.stream()
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);
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break;
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case 2:
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launch_bf16_gemv<2>(
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x_ptr, weight_ptr, bias_ptr, output_ptr, n_int, k_int, stream.stream()
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);
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break;
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case 4:
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launch_bf16_gemv<4>(
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x_ptr, weight_ptr, bias_ptr, output_ptr, n_int, k_int, stream.stream()
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);
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break;
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case 8:
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launch_bf16_gemv<8>(
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x_ptr, weight_ptr, bias_ptr, output_ptr, n_int, k_int, stream.stream()
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);
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break;
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}
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C10_CUDA_CHECK(cudaGetLastError());
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return output;
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}
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} // namespace
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PYBIND11_MODULE(TORCH_EXTENSION_NAME, module) {
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module.def(
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"bf16_gemv",
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&bf16_gemv,
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py::arg("x"),
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py::arg("weight"),
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py::arg("bias") = py::none(),
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"M in {1,2,4,8} BF16 GEMV with FP32 accumulation and optional fused bias"
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);
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}
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