ViperEkura 85dc771460 perf: reduce MMA kernel registers, switch to static smem ... - Move Qa[KD][4] into tile loop (reload from sQ per tile) cutting ~32 resident registers for HEAD_DIM=128 - Replace extern __shared__ with static template-sized smem (no cudaFuncSetAttribute or dynamic allocation needed) - Add __launch_bounds__ with MIN_BLOCKS param, dispatch by HEAD_DIM (hd=128→4, hd=64→6, hd=32→6) - Remove dynamic smem from scalar kernel and C test - Result: hd=128 168→128 regs, 25%→33% occupancy		2026-07-10 00:39:47 +08:00
..
gqa_common.cuh	fix: correct prefill mask index, unify GQA kernel interface	2026-07-06 17:21:23 +08:00
gqa_decode_attn.cu	perf: apply cp.async, XOR swizzle, pre-scaled Q to decode MMA kernel	2026-07-08 16:15:14 +08:00
gqa_decode_attn.cuh	fix: correct prefill mask index, unify GQA kernel interface	2026-07-06 17:21:23 +08:00
gqa_decode_attn_mma.cuh	perf: apply cp.async, XOR swizzle, pre-scaled Q to decode MMA kernel	2026-07-08 16:15:14 +08:00
gqa_mma_utils.cuh	feat: support HEAD_DIM=32 and split extension into loader/ops	2026-07-08 14:14:11 +08:00
gqa_prefill_attn.cu	perf: reduce MMA kernel registers, switch to static smem	2026-07-10 00:39:47 +08:00
gqa_prefill_attn.cuh	perf: reduce MMA kernel registers, switch to static smem	2026-07-10 00:39:47 +08:00
gqa_prefill_attn_mma.cuh	perf: reduce MMA kernel registers, switch to static smem	2026-07-10 00:39:47 +08:00