ViperEkura 69fecaf387 perf: double-buffer KV pipeline and Q direct-to-register in decode ... - Double-buffered KV (STAGES=2) for D<=128: next tile cp.async overlaps current tile MMA compute, hiding global load latency - Q loaded directly from global into mma A-operand registers, removing sQ staging and prologue syncwarp - Predicated cp.async unifies full and partial tile paths, eliminating scalar fallback branch - STAGES=1 fallback for D=256 (double-buffer would exceed smem budget) - Applied to both contiguous and paged decode MMA kernels - ~1.27x average speedup on L20 (sm_89), zero precision loss		2026-07-12 14:14:54 +08:00
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attn_decode_test.cu	perf: double-buffer KV pipeline and Q direct-to-register in decode	2026-07-12 14:14:54 +08:00
attn_paged_decode_test.cu	perf: double-buffer KV pipeline and Q direct-to-register in decode	2026-07-12 14:14:54 +08:00
attn_prefill_test.cu	feat: wire up paged decode CUDA kernel to Python extension	2026-07-11 18:40:49 +08:00
test_utils.cuh	refactor: extract bench_kernel and dispatch_by_head_dim into test_utils	2026-07-12 00:05:04 +08:00