118 lines
4.0 KiB
Plaintext
118 lines
4.0 KiB
Plaintext
// per-KV-head block, K shared in smem, each thread handles hd/32 elements
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#include <cuda_bf16.h>
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#include <cuda_runtime.h>
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#include <cmath>
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#include <cfloat>
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#include <torch/extension.h>
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using bf16 = __nv_bfloat16;
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constexpr int CHUNK = 64;
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__inline__ __device__ float warp_reduce_sum(float val) {
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for (int offset = 16; offset > 0; offset >>= 1)
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val += __shfl_xor_sync(0xFFFFFFFF, val, offset);
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return val;
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}
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__global__ void gqa_decode_attn_kernel(
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const bf16* __restrict__ q_ptr,
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const bf16* __restrict__ k_ptr,
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const bf16* __restrict__ v_ptr,
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const bool* __restrict__ mask_ptr,
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bf16* __restrict__ out_ptr,
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int B, int n_heads, int n_kv_heads, int seq_len, int hd
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) {
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int batch = blockIdx.x / n_kv_heads;
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int kv_head = blockIdx.x % n_kv_heads;
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int group_size = blockDim.y;
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int q_head = kv_head * group_size + threadIdx.y;
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int lane = threadIdx.x;
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int hd_per_thread = hd / 32;
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float q_reg[8];
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int q_off = ((batch * n_heads + q_head) * 1) * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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q_reg[i] = __bfloat162float(q_ptr[q_off + i]);
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int kv_base = ((batch * n_kv_heads + kv_head) * seq_len) * hd;
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int mask_base = batch * seq_len;
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float m = -FLT_MAX, d = 0.0f, acc_reg[8] = {0.0f};
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float scale = rsqrtf((float)hd);
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extern __shared__ __align__(16) bf16 k_smem[];
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for (int chunk_start = 0; chunk_start < seq_len; chunk_start += CHUNK) {
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int this_chunk = min(CHUNK, seq_len - chunk_start);
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int total = this_chunk * hd;
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for (int i = threadIdx.y * 32 + lane; i < total; i += blockDim.x * blockDim.y)
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k_smem[i] = k_ptr[kv_base + chunk_start * hd + i];
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__syncthreads();
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for (int s = 0; s < this_chunk; s++) {
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float partial = 0.0f;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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partial += q_reg[i] * __bfloat162float(k_smem[s * hd + lane * hd_per_thread + i]);
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partial = warp_reduce_sum(partial) * scale;
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if (!mask_ptr[mask_base + chunk_start + s]) partial = -FLT_MAX;
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float new_m = fmaxf(m, partial);
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float alpha = expf(m - new_m);
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float beta = expf(partial - new_m);
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d = d * alpha + beta;
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int v_off = kv_base + (chunk_start + s) * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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acc_reg[i] = acc_reg[i] * alpha + __bfloat162float(v_ptr[v_off + i]) * beta;
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m = new_m;
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}
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__syncthreads();
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}
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int out_off = ((batch * n_heads + q_head) * 1) * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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out_ptr[out_off + i] = __float2bfloat16(acc_reg[i] / d);
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}
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torch::Tensor gqa_decode_attn(
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torch::Tensor q, torch::Tensor k, torch::Tensor v, torch::Tensor mask
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) {
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TORCH_CHECK(q.is_cuda() && k.is_cuda() && v.is_cuda() && mask.is_cuda());
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TORCH_CHECK(q.dtype() == torch::kBFloat16);
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TORCH_CHECK(k.dtype() == torch::kBFloat16);
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TORCH_CHECK(v.dtype() == torch::kBFloat16);
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TORCH_CHECK(mask.dtype() == torch::kBool);
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TORCH_CHECK(q.size(2) == 1, "Q seq_len must be 1");
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int B = q.size(0), n_heads = q.size(1), n_kv = k.size(1);
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int seq_len = k.size(2), hd = q.size(3);
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TORCH_CHECK(hd % 32 == 0, "head_dim must be multiple of 32");
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int group_size = n_heads / n_kv;
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auto out = torch::empty_like(q);
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size_t smem = CHUNK * hd * sizeof(bf16); // K chunk
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dim3 block(32, group_size);
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dim3 grid(B * n_kv);
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gqa_decode_attn_kernel<<<grid, block, smem>>>(
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reinterpret_cast<const bf16*>(q.data_ptr()),
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reinterpret_cast<const bf16*>(k.data_ptr()),
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reinterpret_cast<const bf16*>(v.data_ptr()),
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mask.data_ptr<bool>(),
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reinterpret_cast<bf16*>(out.data_ptr()),
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B, n_heads, n_kv, seq_len, hd
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);
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return out;
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}
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PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
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m.def("gqa_decode_attn", &gqa_decode_attn, "GQA decode v2 (per-KV-head, shared K)");
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}
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