ViperEkura
74e694921c
- K tile 32->64 (new default): fewer barriers, more MMA per stage; generalize tile_at swizzle and load_operand_tile accordingly - 64x128 small-M CTA for m<=64 (2x at 64x4096x4096) - L2 rasterization for crosswise-A layouts (+6..21%) - micro-bench: NT 4096^3 +35%; linear fwd 1.24-1.76x, bwd 1.71-2.27x vs bf16 - add csrc/tests/fp8_test.cu (single MMA demo + GEMM layouts x K-tiles vs CPU reference)
540 lines
26 KiB
Plaintext
540 lines
26 KiB
Plaintext
#pragma once
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// FP8 GEMM device code — pure CUDA, no torch. Mirrors the attention kernel
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// layout (attn_*_mma.cuh): kernels take the FP8Params POD, tile shape and
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// FP8 format ride on compile-time template parameters, and launchers are
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// plain functions usable from both the torch binding and pure C tests.
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#include <cuda_bf16.h>
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#include <cuda_fp8.h>
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#include <cuda_runtime.h>
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#include <type_traits>
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#include "common.h"
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#include "../common/cp_async.cuh"
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#include "../common/mma.cuh"
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#include "../common/reduce.cuh"
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namespace astrai {
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namespace fp8 {
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// m16n8k32 (see astrai::mma_shape<fp8 type>::k in common/mma.cuh)
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constexpr int kMmaK = 32;
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constexpr int kWarps = 8; // 128x128 CTA = 8 warps
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// log2 of a compile-time power of two (for tile_at's swizzle shift).
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template <int N, int Acc = 0>
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struct log2_const : log2_const<(N >> 1), Acc + 1> {};
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template <int Acc>
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struct log2_const<1, Acc> {
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static constexpr int value = Acc;
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};
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// Map the FP8Format enum to the CUDA fp8 element type consumed by mma_sync.
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template <FP8Format Fmt>
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struct fp8_input {
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using type = __nv_fp8_e4m3;
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};
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template <>
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struct fp8_input<FP8Format::E5M2> {
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using type = __nv_fp8_e5m2;
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};
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// ---------------------------------------------------------------------------
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// Shared device helpers
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// ---------------------------------------------------------------------------
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// FP8 MMA lives in the shared astrai::mma_sync template (common/mma.cuh);
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// instantiate it with fp8_input<Fmt>::type. Accumulates in-place: callers
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// pass the same accumulator array as both `d` and `c`.
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// warp_reduce_max / atomic_max_float (quantize amax) live in
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// common/reduce.cuh; the cp.async pipeline primitives (predicated 16-byte
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// copy, commit_group, wait_group + runtime dispatch) in common/cp_async.cuh.
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// ---------------------------------------------------------------------------
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// Quantize kernel: BF16 -> FP8 (E4M3 or E5M2), fused amax over raw values.
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// ---------------------------------------------------------------------------
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// Convert one packed bf16 pair to one packed fp8 pair. amax sees the *raw*
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// (unscaled) values; the stored bytes see value * inv. Bit-identical to the
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// scalar __nv_fp8_*(q) constructor path (round-nearest-even + satfinite).
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template <FP8Format Fmt>
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__device__ __forceinline__ unsigned quantize2(unsigned pair, float inv,
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float& amax) {
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const float lo = __bfloat162float(__ushort_as_bfloat16(pair & 0xffffu));
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const float hi = __bfloat162float(__ushort_as_bfloat16(pair >> 16));
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amax = fmaxf(amax, fmaxf(fabsf(lo), fabsf(hi)));
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constexpr __nv_fp8_interpretation_t kFmt =
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Fmt == FP8Format::E5M2 ? __NV_E5M2 : __NV_E4M3;
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return static_cast<unsigned>(
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__nv_cvt_float2_to_fp8x2(make_float2(lo * inv, hi * inv),
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__NV_SATFINITE, kFmt));
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}
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template <FP8Format Fmt>
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__global__ void fp8_quantize_kernel(FP8Params p) {
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const float inv = 1.0f / *p.scale_a;
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const auto* x = reinterpret_cast<const __nv_bfloat16*>(p.a_ptr);
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void* x8 = p.out_ptr;
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float* amax = p.amax_a;
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float local_amax = 0.0f;
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const int64_t stride = (int64_t)blockDim.x * gridDim.x;
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// Vectorized body: 8 bf16 (16B load) -> 8 fp8 (8B store) per step. Torch
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// allocations are >=16B aligned and the binding passes freshly allocated
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// contiguous buffers, so element 0 keeps the uint4/uint2 accesses
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// natural; a misaligned base (contiguous view with an odd storage
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// offset) falls back to the scalar loop below via total_vec = 0.
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const bool aligned =
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((reinterpret_cast<uintptr_t>(x) | reinterpret_cast<uintptr_t>(x8))
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& 15) == 0;
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const int64_t total_vec = aligned ? p.total / 8 : 0;
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const uint4* xv = reinterpret_cast<const uint4*>(x);
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uint2* o8 = reinterpret_cast<uint2*>(x8);
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for (int64_t i = blockIdx.x * blockDim.x + threadIdx.x; i < total_vec;
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i += stride) {
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const uint4 v = xv[i];
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const unsigned pair[4] = {v.x, v.y, v.z, v.w};
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unsigned packed[2] = {0u, 0u};
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#pragma unroll
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for (int j = 0; j < 4; ++j)
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packed[j >> 1] |= quantize2<Fmt>(pair[j], inv, local_amax)
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<< (16 * (j & 1));
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o8[i] = make_uint2(packed[0], packed[1]);
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}
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// Scalar tail (and full fallback for misaligned bases).
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for (int64_t i = total_vec * 8 + blockIdx.x * blockDim.x + threadIdx.x;
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i < p.total; i += stride) {
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const float f = __bfloat162float(x[i]);
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local_amax = fmaxf(local_amax, fabsf(f));
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if constexpr (Fmt == FP8Format::E5M2) {
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reinterpret_cast<__nv_fp8_e5m2*>(x8)[i] = __nv_fp8_e5m2(f * inv);
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} else {
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reinterpret_cast<__nv_fp8_e4m3*>(x8)[i] = __nv_fp8_e4m3(f * inv);
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}
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}
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if (amax) {
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local_amax = warp_reduce_max(local_amax);
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__shared__ float slots[32];
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if ((threadIdx.x & 31) == 0) slots[threadIdx.x >> 5] = local_amax;
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__syncthreads();
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if (threadIdx.x == 0) {
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float v = 0.0f;
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for (int w = 0; w < (blockDim.x >> 5); ++w) v = fmaxf(v, slots[w]);
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atomic_max_float(amax, v);
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}
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}
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}
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// Swizzled address inside a flat [rows * K] staging tile: the 16-byte chunk
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// index is XORed with a row-dependent slice so a warp's fragment load (8
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// consecutive rows x 16B) hits all 32 banks exactly once. With kChunks
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// power-of-two chunks per row, the XOR source is the top log2(kChunks) bits
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// of the row index within each group of 8:
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// kChunks=2 -> row bits [3] (K=32: rows r and r+4 diverge)
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// kChunks=4 -> row bits [2:1] (K=64: rows diverge every 2)
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// kChunks=8 -> row bits [2:0] (K=128: every row)
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// (row word-stride is K/4 words = 4*kChunks, so unswizzled rows r and
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// r + 8/kChunks collide mod 32 banks; the XOR spreads the 8 rows of one
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// ldmatrix matrix across the 8 distinct 4-bank groups.) Chunks stay
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// contiguous, so the cp.async 16B staging path is unaffected.
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template <int K, typename T8>
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__device__ __forceinline__ T8* tile_at(T8* tile, int row, int col) {
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constexpr int kChunks = K / 16; // 16B chunks per row
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static_assert(kChunks >= 1 && (kChunks & (kChunks - 1)) == 0,
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"swizzle needs a power-of-two 16B-chunk count");
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constexpr int kShift = 3 - log2_const<kChunks>::value;
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return tile + row * K
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+ ((((col >> 4) ^ ((row >> kShift) & (kChunks - 1))) << 4)
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+ (col & 15));
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}
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// Stage-load one GEMM operand into the canonical flat [rows * K] shared tile
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// (addressing via tile_at, so stores land in the swizzled layout). The
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// transpose is folded into the staging step via a CUTLASS-style crosswise
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// layout: RowMajor (stored [rows][contract]) copies 16-byte K-contiguous runs
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// with cp.async, while ColMajor (stored [contract][rows]) reads 16-byte runs
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// along the operand's contiguous non-contract dim and scatters them across
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// the tile's rows. RowsTile is the tile's row capacity (kBlockM / kBlockN)
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// and kThreads the CTA size; the runtime `rows` bound may be smaller (tail
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// predication). `block_row` is this block's origin in the operand's row dim.
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template <typename T8, int K, typename Layout, int RowsTile, int kThreads>
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__device__ __forceinline__ void load_operand_tile(
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T8* tile, const T8* __restrict__ operand, int64_t rows,
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int64_t contract, int64_t ld, int tid, int64_t k_base,
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int64_t block_row) {
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constexpr int kChunks = K / 16;
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static_assert(RowsTile * kChunks % kThreads == 0,
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"tile chunks must divide evenly across threads");
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constexpr int kCpt = RowsTile * kChunks / kThreads; // chunks per thread
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if constexpr (std::is_same_v<Layout, ColMajor>) {
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// Operand stored [contract][rows]: contiguous along the non-contract
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// dim. Each thread scatters one 16-byte run per K/32 pass; when the
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// tile has more 16-row groups than warps (RowsTile > kThreads/2),
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// each thread covers several groups.
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constexpr int kWarpsTile = kThreads / 32;
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constexpr int kGroups = RowsTile / 16;
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static_assert(kGroups % kWarpsTile == 0,
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"row groups must divide evenly across warps");
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#pragma unroll
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for (int g = 0; g < kGroups / kWarpsTile; ++g) {
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const int rg = (tid >> 5) + g * kWarpsTile;
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const int kl = tid & 31; // byte column within a 32B pass
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const int64_t r0 = block_row + rg * 16;
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#pragma unroll
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for (int pass = 0; pass < K / 32; ++pass) {
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const int col = kl + pass * 32;
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const int64_t k_idx = k_base + col;
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const auto* src = operand + k_idx * ld + r0;
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if (k_idx < contract && r0 + 15 < rows &&
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(reinterpret_cast<uintptr_t>(src) & 15) == 0) {
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const uint4 v = *reinterpret_cast<const uint4*>(src);
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const auto* bytes = reinterpret_cast<const T8*>(&v);
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// Scatter 16 bytes along the tile rows through tile_at's
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// swizzle. Rows sharing a physical chunk form groups of
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// (8 / kChunks) consecutive rows (see tile_at), so each
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// group is one tile_at address plus a K-byte row stride.
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constexpr int kGrp = 8 / kChunks;
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#pragma unroll
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for (int j = 0; j < 16 / kGrp; ++j) {
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T8* p = tile_at<K>(tile,
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rg * 16 + j * kGrp, col);
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#pragma unroll
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for (int i = 0; i < kGrp; ++i)
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p[i * K] = bytes[j * kGrp + i];
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}
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} else {
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// Predicated fallback: same layout, byte-granular gather.
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#pragma unroll
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for (int i = 0; i < 16; ++i) {
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const int64_t r_idx = r0 + i;
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*tile_at<K>(tile, rg * 16 + i, col) =
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(r_idx < rows && k_idx < contract)
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? operand[k_idx * ld + r_idx]
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: T8(0.0f);
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}
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}
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}
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}
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} else {
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// Operand stored [rows][contract]: contiguous along the contract dim.
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// Linear chunk mapping: thread covers kCpt consecutive 16B chunks of
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// one row (K=64: a contiguous 32B pair; K=32: a single chunk).
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const int r = tid / (kChunks / kCpt);
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#pragma unroll
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for (int j = 0; j < kCpt; ++j) {
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const int c = ((tid % (kChunks / kCpt)) * kCpt + j) * 16;
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const int64_t row = block_row + r;
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const auto* src = operand + row * ld + k_base + c;
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T8* dst = tile_at<K>(tile, r, c);
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if (row < rows && k_base + c + 15 < contract &&
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(reinterpret_cast<uintptr_t>(src) & 15) == 0) {
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astrai::cp_async_16(dst, src, true);
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} else {
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#pragma unroll
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for (int i = 0; i < 16; ++i)
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dst[i] = row < rows && k_base + c + i < contract
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? src[i]
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: T8(0.0f);
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}
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}
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}
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}
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// ---------------------------------------------------------------------------
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// Pre-quantized GEMM kernel: FP8 A/B read straight into shared memory, FP32
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// accumulation, BF16 or FP8 output. The input format follows Traits; the
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// tile is compact (row = kK bytes) so MMA fragments read directly — no
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// in-kernel transpose of the operands (the binding handles transposes).
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// ---------------------------------------------------------------------------
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// Swizzled 16B-chunk address (tile_at's layout) as a raw shared-memory
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// pointer for ldmatrix. Valid for kK in {32, 64} (the swizzle itself lives
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// only in tile_at; this wrapper just converts the element address).
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template <typename T8, int kK>
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__device__ __forceinline__ unsigned frag_addr(const T8* tile, int row,
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int chunk) {
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static_assert(kK == 32 || kK == 64,
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"fragment swizzle offsets assume kK in {32, 64}");
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return __cvta_generic_to_shared(tile_at<kK>(tile, row, chunk << 4));
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}
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// LayoutA / LayoutB tag the operands' storage (CUTLASS-style, see common.h):
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// A RowMajor = [M][K] / ColMajor = [K][M]; B RowMajor = [K][N] /
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// ColMajor = [N][K]. The kernel always computes
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// out[m][n] = sum_p tileA[m][p] * tileB[n][p]
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// with the tiles materialized in the canonical [M][kK] / [N][kK] layout, so the
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// MMA fragments are read identically regardless of layout. The tags only
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// change how the stage-load gathers the operand from global memory:
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// A ColMajor: tileA[m][p] = a[p*a_ld + m]; A RowMajor: a[m*a_ld + p]
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// B RowMajor: tileB[n][p] = b[p*b_ld + n]; B ColMajor: b[n*b_ld + p]
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// BlockM x BlockN CTA as (BlockM/64) x (BlockN/32) warps of 64x32 warp tiles
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// (mt x nt = 4x4 MMA each). The 64x128 variant runs 4 warps / 128 threads and
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// exists for small-M calls: m <= 64 wastes half of every 128-row CTA, so the
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// launcher dispatches to it there (see launch_fp8_gemm).
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template <typename Traits, bool OutFp8 = false, typename LayoutA = RowMajor, typename LayoutB = RowMajor>
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__global__ void __launch_bounds__(
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(Traits::kBlockM / 64) * (Traits::kBlockN / 32) * 32, 2)
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fp8_gemm_kernel(FP8Params p) {
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using T8 = std::conditional_t<Traits::kIsE5M2, __nv_fp8_e5m2, __nv_fp8_e4m3>;
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constexpr int kBlockM = Traits::kBlockM;
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constexpr int kBlockN = Traits::kBlockN;
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constexpr int kK = Traits::kK;
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constexpr int kStages = Traits::kStages;
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constexpr int kCtaThreads = (kBlockM / 64) * (kBlockN / 32) * 32;
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static_assert(kStages >= 1 && kStages <= 8,
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"FP8 GEMM stages must be in the range [1, 8]");
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// Tiles are flat [rows * kK] with a 16B-chunk XOR swizzle (tile_at):
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// ldmatrix reads whole 16B chunks through the same mapping the staging
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// writes, and the swizzle removes the bank conflict the unswizzled
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// 8-word row stride caused (see tile_at).
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__shared__ __align__(16) T8 a_smem[kStages][kBlockM * kK];
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__shared__ __align__(16) T8 b_smem[kStages][kBlockN * kK];
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const auto* a = reinterpret_cast<const T8*>(p.a_ptr);
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const auto* b = reinterpret_cast<const T8*>(p.b_ptr);
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auto* out_bf16 = reinterpret_cast<__nv_bfloat16*>(p.out_ptr);
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auto* out_fp8 = reinterpret_cast<__nv_fp8_e4m3*>(p.out_ptr);
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const int64_t m = p.m, n = p.n, k = p.k;
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const int64_t a_ld = p.a_ld, b_ld = p.b_ld;
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const int tid = threadIdx.x;
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const int warp = tid >> 5;
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const int lane = tid & 31;
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const int group = lane >> 2;
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const int thread_in_group = lane & 3;
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// L2-friendly rasterization (CUTLASS-style grouped launch order): remap
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// the linear block id so consecutive CTAs cover a group of kGroupM M-tiles
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// before advancing along N. All CTAs of one group share the same B column
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// stripe, so B tiles stay hot in L2 across the wave (the default
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// N-fastest order makes each wave touch every B tile instead).
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// Measured win for the A-crosswise layouts (10-21% at K>=2048) and loss
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// for A-congruous (-17..20%, A's cp.async stream prefers the N-fastest
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// order) — so the branch follows LayoutA.
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constexpr int kGroupM = 8;
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int block_m, block_n;
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if constexpr (std::is_same_v<LayoutA, ColMajor>) {
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const int blocks_m = gridDim.y;
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const int bid = blockIdx.y * gridDim.x + blockIdx.x;
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const int group_first_m = (bid / (kGroupM * gridDim.x)) * kGroupM;
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const int group_rows =
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min(blocks_m - group_first_m, kGroupM); // M-tail group is short
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block_m = group_first_m + bid % group_rows;
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block_n = (bid % (kGroupM * gridDim.x)) / group_rows;
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} else {
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block_m = blockIdx.y;
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block_n = blockIdx.x;
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}
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// 128x128 CTA = 8 warps as 2x4 warp tiles of 64x32 (mt x nt = 4x4 MMA).
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constexpr int warps_n = kBlockN / 32;
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const int warp_m = warp / warps_n;
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const int warp_n = warp % warps_n;
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const int64_t row_base =
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(int64_t)block_m * kBlockM + warp_m * 64 + group;
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const int64_t output_col =
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(int64_t)block_n * kBlockN + warp_n * 32 + thread_in_group * 2;
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const int a_row0 = warp_m * 64; // + mt * 16 in the loop
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const int b_row0 = warp_n * 32; // + nt * 8
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const float sa = *p.scale_a;
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const float sb = *p.scale_b;
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float acc[4][4][4] = {}; // [nt][mt][acc]
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// Both operands are staged into the canonical [M][kK] / [N][kK] shared
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// tiles regardless of their global layout (see load_operand_tile), so the
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// MMA fragment reads below stay unchanged across the four layout
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// combinations. A's tag already names the operand view ([M][K] =
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// [rows][contract]); B's tag is relative to the canonical [K][N], so the
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// stage-load sees its transpose (transpose_layout_t, see common.h).
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auto load_tile = [&](int stage, int64_t k_base) {
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load_operand_tile<T8, kK, LayoutA, kBlockM, kCtaThreads>(
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a_smem[stage], a, m, k, a_ld, tid, k_base,
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(int64_t)block_m * kBlockM);
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load_operand_tile<T8, kK, transpose_layout_t<LayoutB>, kBlockN,
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kCtaThreads>(
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b_smem[stage], b, n, k, b_ld, tid, k_base,
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(int64_t)block_n * kBlockN);
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};
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const int64_t tile_count = (k + kK - 1) / kK;
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// Per-lane ldmatrix row/chunk selectors for common/mma.cuh's
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// ldmatrix_*_lane (the fragment tiles are XOR-swizzled per 16B chunk, so
|
|
// each lane computes its own row/chunk address). Layout contract for fp8
|
|
// m16n8k32 (values packed two-per-b16 slot, K-contiguous rows):
|
|
// x4 (A fragment): lane i points at tile row (i>>3 & 1)*8 + (i&7) of
|
|
// chunk (k_seg*2 + (i>>4)); reg j = matrix j = [row g][tig*4..+3] in
|
|
// the order (rows 0-7 c, rows 8-15 c, rows 0-7 c+1, rows 8-15 c+1) —
|
|
// exactly the mma.sync A operand layout.
|
|
// x2 (B fragment): lane i points at tile row (i&7) of chunk
|
|
// (k_seg*2 + ((i>>3) & 1)); reg j = [row(n) g][tig*4..+3] chunk c/c+1
|
|
// — exactly the mma.sync B operand layout (col operand, K-contiguous).
|
|
const int r7 = lane & 7; // row within the 8-row matrix
|
|
const int rh8 = (lane >> 3) & 1; // +8 rows (A: lanes 8-15, 24-31)
|
|
const int rh16 = lane >> 4; // +1 chunk (A: lanes 16-31; B uses rh8)
|
|
|
|
// Prime the pipeline. Each committed group occupies one circular shared
|
|
// memory stage; the loop also handles K dimensions smaller than kStages.
|
|
#pragma unroll
|
|
for (int stage = 0; stage < kStages; ++stage) {
|
|
if (stage < tile_count) {
|
|
load_tile(stage, static_cast<int64_t>(stage) * kK);
|
|
astrai::cp_async_commit_group();
|
|
}
|
|
}
|
|
|
|
for (int64_t tile_index = 0; tile_index < tile_count; ++tile_index) {
|
|
const int stage = static_cast<int>(tile_index % kStages);
|
|
const int64_t remaining = tile_count - tile_index - 1;
|
|
|
|
// Keep up to kStages - 1 younger groups in flight while making the
|
|
// oldest group (the current stage) ready for consumption.
|
|
const int keep_groups =
|
|
remaining < kStages - 1 ? static_cast<int>(remaining) : kStages - 1;
|
|
astrai::cp_async_wait_group_dispatch<kStages - 1>(keep_groups);
|
|
// Barrier 1: every thread's cp.async for this stage is complete
|
|
// before any thread reads tiles written by other threads.
|
|
__syncthreads();
|
|
|
|
// 4 ldmatrix.x2 (B) + 4 ldmatrix.x4 (A) feed 16 mma.sync per k_seg —
|
|
// 0.5 load instructions per MMA, versus 4.5 scalar LDS per MMA in
|
|
// the 128x64-tile version (the kernel was LSU-issue-bound there).
|
|
constexpr int kSegs = kK / kMmaK;
|
|
// B fragments double-buffered across k_segs: the next k_seg's B load
|
|
// is issued before the current k_seg's MMA sequence, so its LDS
|
|
// latency hides behind the A pipeline + tensor-pipe work (same trick
|
|
// as the A mt+1 prefetch below; costs kSegs x 8 registers).
|
|
unsigned b_frag[2][4][2];
|
|
#pragma unroll
|
|
for (int nt = 0; nt < 4; ++nt) {
|
|
const int row = b_row0 + nt * 8 + r7;
|
|
astrai::ldmatrix_x2_lane(b_frag[0][nt],
|
|
frag_addr<T8, kK>(b_smem[stage], row, rh8));
|
|
}
|
|
#pragma unroll
|
|
for (int k_seg = 0; k_seg < kSegs; ++k_seg) {
|
|
const int bcur = k_seg & 1, bnext = bcur ^ 1;
|
|
if (k_seg + 1 < kSegs) {
|
|
#pragma unroll
|
|
for (int nt = 0; nt < 4; ++nt) {
|
|
const int row = b_row0 + nt * 8 + r7;
|
|
astrai::ldmatrix_x2_lane(b_frag[bnext][nt],
|
|
frag_addr<T8, kK>(b_smem[stage], row,
|
|
(k_seg + 1) * 2 + rh8));
|
|
}
|
|
}
|
|
// Software-pipelined A fragments: the ldmatrix.x4 for row mt+1
|
|
// is issued before the MMAs consuming row mt, so the LDS fixed
|
|
// latency hides behind tensor-pipe work (cuts the `wait` stall,
|
|
// ~2.3 cycles/issue before this). Costs 4 extra registers.
|
|
unsigned a_frag[5][4];
|
|
astrai::ldmatrix_x4_lane(a_frag[0],
|
|
frag_addr<T8, kK>(a_smem[stage], a_row0 + rh8 * 8 + r7,
|
|
k_seg * 2 + rh16));
|
|
#pragma unroll
|
|
for (int mt = 0; mt < 4; ++mt) {
|
|
if (mt < 3)
|
|
astrai::ldmatrix_x4_lane(a_frag[mt + 1],
|
|
frag_addr<T8, kK>(
|
|
a_smem[stage],
|
|
a_row0 + (mt + 1) * 16 + rh8 * 8 + r7,
|
|
k_seg * 2 + rh16));
|
|
#pragma unroll
|
|
for (int nt = 0; nt < 4; ++nt)
|
|
astrai::mma_sync<T8>(acc[nt][mt], a_frag[mt],
|
|
b_frag[bcur][nt], acc[nt][mt]);
|
|
}
|
|
}
|
|
// Barrier 2: every thread finished reading this stage's tiles before
|
|
// the prefetch for the (i+kStages)-th tile overwrites them.
|
|
__syncthreads();
|
|
if (tile_index + kStages < tile_count) {
|
|
load_tile(stage, (tile_index + kStages) * kK);
|
|
astrai::cp_async_commit_group();
|
|
}
|
|
}
|
|
|
|
const float output_scale = sa * sb;
|
|
const float o8_scale = OutFp8 ? output_scale * *p.out_scale : 0.0f;
|
|
#pragma unroll
|
|
for (int nt = 0; nt < 4; ++nt) {
|
|
const int64_t col = output_col + nt * 8;
|
|
// Per-row store: FP8 packs two adjacent columns into one 16-bit
|
|
// write, BF16 into one 32-bit __nv_bfloat162 (single cvt+pack
|
|
// instruction); boundary or unaligned columns fall back to scalar
|
|
// converts so a pack never crosses the row edge or misaligns.
|
|
auto store_out = [&](int64_t row, float v0, float v1) {
|
|
if (row >= m) return;
|
|
if constexpr (OutFp8) {
|
|
if (col + 1 < n) {
|
|
*reinterpret_cast<unsigned short*>(out_fp8 + row * n + col) =
|
|
static_cast<unsigned short>(__nv_cvt_float2_to_fp8x2(
|
|
make_float2(v0 * o8_scale, v1 * o8_scale),
|
|
__NV_SATFINITE, __NV_E4M3));
|
|
} else {
|
|
out_fp8[row * n + col] = __nv_fp8_e4m3(v0 * o8_scale);
|
|
}
|
|
} else {
|
|
auto* dst = out_bf16 + row * n + col;
|
|
if (col + 1 < n &&
|
|
(reinterpret_cast<uintptr_t>(dst) & 3) == 0) {
|
|
*reinterpret_cast<__nv_bfloat162*>(dst) =
|
|
__floats2bfloat162_rn(v0 * output_scale,
|
|
v1 * output_scale);
|
|
} else {
|
|
dst[0] = __float2bfloat16(v0 * output_scale);
|
|
if (col + 1 < n)
|
|
dst[1] = __float2bfloat16(v1 * output_scale);
|
|
}
|
|
}
|
|
};
|
|
#pragma unroll
|
|
for (int mt = 0; mt < 4; ++mt) {
|
|
const int64_t row0 = row_base + mt * 16;
|
|
float* tile_acc = acc[nt][mt];
|
|
if (col < n) {
|
|
store_out(row0, tile_acc[0], tile_acc[1]);
|
|
store_out(row0 + 8, tile_acc[2], tile_acc[3]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// ---------------------------------------------------------------------------
|
|
// Launchers — pure CUDA (no torch), usable from the binding and pure C tests.
|
|
// ---------------------------------------------------------------------------
|
|
|
|
template <FP8Format Fmt>
|
|
void launch_fp8_quantize(const FP8Params& p, cudaStream_t stream) {
|
|
constexpr int kThreads = 256;
|
|
// One block per 256 vectors (8 elements each); at least one block so the
|
|
// scalar tail of a tiny / misaligned tensor is still covered.
|
|
int64_t blocks = (p.total / 8 + kThreads - 1) / kThreads;
|
|
if (blocks < 1) blocks = 1;
|
|
fp8_quantize_kernel<Fmt><<<blocks, kThreads, 0, stream>>>(p);
|
|
}
|
|
|
|
// Pre-quantized GEMM tile config: 128x128 CTA (8 warps x 64x32 warp tiles).
|
|
// kK selects the K tile (32 or 64; 64 halves the __syncthreads count per K
|
|
// and doubles the MMA work per stage, at 2x the smem per stage — measured
|
|
// 10-35% across shapes, so 64 is the default). Stages=2 with kK=64 keeps the
|
|
// pipeline at 32KB smem; deeper pipelines only win on K >= 4096 squares and
|
|
// lose elsewhere. LayoutA/LayoutB mirror the kernel template (defaults keep
|
|
// the NN layout: out = a @ b). m <= 64 dispatches to the 64x128 CTA — a
|
|
// 128-row CTA would waste half its MMA work on predicated-off rows.
|
|
template <FP8Format Fmt, bool OutFp8 = false, typename LayoutA = RowMajor,
|
|
typename LayoutB = RowMajor, int kK = 64, int Stages = 2>
|
|
void launch_fp8_gemm(const FP8Params& p, cudaStream_t stream) {
|
|
dim3 grid((p.n + 127) / 128, (p.m + 127) / 128);
|
|
if (p.m <= 64) {
|
|
using Traits = Fp8GemmTraits<Fmt, 64, 128, kK, Stages>;
|
|
fp8_gemm_kernel<Traits, OutFp8, LayoutA, LayoutB>
|
|
<<<grid, (64 / 64) * (128 / 32) * 32, 0, stream>>>(p);
|
|
} else {
|
|
using Traits = Fp8GemmTraits<Fmt, 128, 128, kK, Stages>;
|
|
fp8_gemm_kernel<Traits, OutFp8, LayoutA, LayoutB>
|
|
<<<grid, (128 / 64) * (128 / 32) * 32, 0, stream>>>(p);
|
|
}
|
|
}
|
|
|
|
} // namespace fp8
|
|
} // namespace astrai
|