178 lines
6.7 KiB
Plaintext
178 lines
6.7 KiB
Plaintext
#pragma once
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#include <cfloat>
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#include <cuda_bf16.h>
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#include "attn_common.h"
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#include "attn_mma_utils.cuh"
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using bf16 = __nv_bfloat16;
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// Split-K (FlashDecoding) tensor-core decode via GQA head-packing.
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//
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// Decode has q_len == 1, so S = q @ K^T is a GEMV per head — no tensor-core
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// work on its own. But GQA gives us G = q_head / kv_head query heads that all
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// share one kv_head. We pack those G heads into the M=16 rows of
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// mma.sync.m16n8k16, turning G independent GEMVs into a single GEMM that
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// reuses each loaded K/V tile across all G heads (K/V load is the decode
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// bottleneck, so the reuse is the win, not the flops). The KV sequence is
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// partitioned across gridDim.z blocks so that a decode with only
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// batch*kv_head independent tasks can fill all SMs. Each (batch, kv_head,
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// split) block computes an UN-normalised partial (Oacc, m, l) over its KV
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// slice; the combine kernel below reduces across splits. Fixes the "grid too
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// small" bottleneck (0.04 waves/SM → many blocks) for long-context,
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// small-batch decode.
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template <int HEAD_DIM, int BC, int STAGES = 2>
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__global__ void attn_decode_split_kv_mma_kernel(AttentionParams<bf16> p) {
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constexpr int KD = HEAD_DIM / 16;
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constexpr int NC8 = BC / 8;
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constexpr int KT2 = BC / 16;
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constexpr int DN8 = HEAD_DIM / 8;
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constexpr int LD = HEAD_DIM;
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constexpr int SWIZ_MASK = (HEAD_DIM >= 64) ? 7 : (HEAD_DIM / 8 - 1);
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constexpr int VEC = 8;
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constexpr int TOTAL = BC * HEAD_DIM;
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const int lane = threadIdx.x;
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const int gid = lane >> 2;
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const int tid4 = lane & 3;
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const int kv_head = blockIdx.x;
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const int batch = blockIdx.y;
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const int split = blockIdx.z;
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const int G = p.q_head / p.kv_head;
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const int q_head0 = kv_head * G;
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// Double-buffered shared memory for K/V (no sQ needed — Q goes direct
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// from global to registers).
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__shared__ __align__(16) bf16 sK[STAGES * BC * LD];
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__shared__ __align__(16) bf16 sV[STAGES * BC * LD];
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// ---- Load Q directly from global into mma A-operand registers ----
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const int q_base = batch * p.q_stride_b + q_head0 * p.q_stride_h;
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const int qra = gid;
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const int qrb = gid + 8;
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const bool va = qra < G, vb = qrb < G;
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unsigned Qa[KD][4];
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load_q_mma_frags<KD>(p.q + q_base, p.q_stride_h, p.q_stride_d,
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qra, qrb, va, vb, tid4, Qa);
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float Oacc[DN8][4];
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#pragma unroll
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for (int j = 0; j < DN8; j++)
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Oacc[j][0] = Oacc[j][1] = Oacc[j][2] = Oacc[j][3] = 0.0f;
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float m0 = -FLT_MAX, m1 = -FLT_MAX, l0 = 0.0f, l1 = 0.0f;
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// KV: stride-based base — [batch, kv_head, kv_len, head_dim]
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const int kv_base = batch * p.kv_stride_b + kv_head * p.kv_stride_h;
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const int mask_batch_base = batch * p.mask_b_stride;
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const int tiles_total = (p.kv_len + BC - 1) / BC;
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const int tiles_per_split = (tiles_total + p.num_splits - 1) / p.num_splits;
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const int ti_begin = split * tiles_per_split;
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const int ti_end = min(tiles_total, ti_begin + tiles_per_split);
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const int has_mask = p.use_mask && p.mask;
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// ---- Load tile lambda: predicated cp.async, unified full/partial ----
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auto load_tile = [&](int ti, int buf) {
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int kv0 = ti * BC;
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bf16* dK = sK + buf * BC * LD;
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bf16* dV = sV + buf * BC * LD;
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#pragma unroll
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for (int i = lane * VEC; i < TOTAL; i += 32 * VEC) {
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int r = i / HEAD_DIM, d = i % HEAD_DIM;
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int kc = kv0 + r;
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bool valid = kc < p.kv_len;
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int off = r * LD + swiz_col(d, r, SWIZ_MASK);
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// KV stride-based: contiguous within head_dim (stride_d == 1 typically)
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int g_off = kv_base + kc * p.kv_stride_l + d * p.kv_stride_d;
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cp_async_16_pred(&dK[off], &p.k[g_off], valid);
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cp_async_16_pred(&dV[off], &p.v[g_off], valid);
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}
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cp_async_commit();
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};
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// ---- Prologue: issue first tile load ----
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if (ti_begin < ti_end) {
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load_tile(ti_begin, 0);
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}
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for (int ti = ti_begin; ti < ti_end; ti++) {
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constexpr int BUF_MASK = (STAGES > 1) ? (STAGES - 1) : 0;
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int buf = (ti - ti_begin) & BUF_MASK;
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// Wait for current tile, then issue next tile's prefetch (overlaps
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// with this tile's compute). Single syncwarp covers both hazards.
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// When STAGES==1, no prefetch — load happens at end of prior iter.
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cp_async_wait_group<0>();
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__syncwarp();
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if constexpr (STAGES > 1) {
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if (ti + 1 < ti_end)
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load_tile(ti + 1, (ti + 1 - ti_begin) & BUF_MASK);
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}
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const bf16* bK = sK + buf * BC * LD;
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const bf16* bV = sV + buf * BC * LD;
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int kv0 = ti * BC;
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float Sacc[NC8][4];
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mma_compute_scores<KD, NC8>(Qa, bK, LD, SWIZ_MASK, lane, Sacc);
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#pragma unroll
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for (int n8 = 0; n8 < NC8; n8++)
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Sacc[n8][0] *= p.scale, Sacc[n8][1] *= p.scale,
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Sacc[n8][2] *= p.scale, Sacc[n8][3] *= p.scale;
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// Decode: q_len=1, so qrow0=qrow1=0, mask_q_stride irrelevant
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int maxc = (p.causal_offset >= 0) ? min(p.kv_len, p.causal_offset + 1) : p.kv_len;
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mma_softmax_tile<NC8, DN8>(kv0, maxc, maxc,
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0, 0,
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mask_batch_base, 0,
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batch,
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p.mask, has_mask,
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Sacc, Oacc, m0, m1, l0, l1, lane);
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mma_pv_accumulate<DN8, KT2>(Sacc, bV, LD, SWIZ_MASK, lane, Oacc);
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__syncwarp();
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if constexpr (STAGES == 1) {
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if (ti + 1 < ti_end)
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load_tile(ti + 1, 0);
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}
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}
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// ---- write UN-normalised partials for this split ----
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auto split_slot = [&](int h) -> size_t {
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size_t bh = (size_t)batch * p.q_head + h;
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return bh * p.num_splits + split;
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};
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#pragma unroll
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for (int dn8 = 0; dn8 < DN8; dn8++) {
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int d = dn8 * 8 + 2 * tid4;
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int r0 = gid, r1 = gid + 8;
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if (r0 < G) {
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int h = q_head0 + r0;
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float* op = p.o_part + split_slot(h) * HEAD_DIM;
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op[d] = Oacc[dn8][0];
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op[d + 1] = Oacc[dn8][1];
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}
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if (r1 < G) {
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int h = q_head0 + r1;
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float* op = p.o_part + split_slot(h) * HEAD_DIM;
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op[d] = Oacc[dn8][2];
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op[d + 1] = Oacc[dn8][3];
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}
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}
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if (tid4 == 0) {
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int r0 = gid, r1 = gid + 8;
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if (r0 < G) {
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int h = q_head0 + r0;
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float* mp = p.ml_part + split_slot(h) * 2;
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mp[0] = m0; mp[1] = l0;
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}
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if (r1 < G) {
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int h = q_head0 + r1;
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float* mp = p.ml_part + split_slot(h) * 2;
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mp[0] = m1; mp[1] = l1;
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}
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}
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}
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