#include "attn_prefill_split_q.cuh" #include "attn_entry_utils.cuh" #ifndef ASTRAI_NO_MMA #include "attn_prefill_split_q_mma.cuh" #endif template static void dispatch_prefill(AttentionParams& p) { #ifndef ASTRAI_NO_MMA constexpr int WARPS = 4, BR = 16; // KV tile: bigger tiles amortize the per-tile cp.async wait + barrier + // loop overhead over more tensor-core work (this kernel is latency-bound, // not compute/bandwidth-bound), so BC=32 wins ~6-8% over BC=16 for // D<=128. D=256 stays at 16: BC=32 double-buffered would need 64KB smem, // over the 48KB static cap. constexpr int BC = (HEAD_DIM <= 128) ? 32 : 16; dim3 grid((p.q_len + BR * WARPS - 1) / (BR * WARPS), p.q_head, p.batch); dim3 block(WARPS * 32, 1, 1); // Static shared memory — double-buffered K/V only (no sQ: Q goes direct // to registers). 2*BC*LD bf16 each for sK and sV → 4*BC*HEAD_DIM*2 bytes. // Occupancy is smem-capped: D=64→3 blocks/SM (16KB), D=128→1 (32KB), // D=256→1 (32KB, BC=16). attn_prefill_split_q_mma_kernel<<>>(p); #else constexpr int G = 8, ROWS = 32, P_BC = 32; dim3 grid((p.q_len + ROWS - 1) / ROWS, p.q_head, p.batch); dim3 block(G, ROWS, 1); attn_prefill_split_q_kernel_t<<>>(p); #endif } torch::Tensor attn_prefill( torch::Tensor q, torch::Tensor k, torch::Tensor v, c10::optional mask, int64_t causal_offset, double scale, int64_t layout ) { AttentionParams p; attn_pack_params(q, k, v, mask, causal_offset, scale, layout, p); TORCH_CHECK(p.head_dim % 16 == 0, "head_dim must be multiple of 16"); auto O = torch::empty_strided(q.sizes(), q.strides(), q.options()); auto O_view = (layout == 1) ? O.transpose(1, 2) : O; p.o = (bf16*)O_view.data_ptr(); DISPATCH_HEAD_DIM(p.head_dim, dispatch_prefill, p); return O; } PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) { m.def("attn_prefill", &attn_prefill, py::arg("q"), py::arg("k"), py::arg("v"), py::arg("mask") = py::none(), py::arg("causal_offset") = -1, py::arg("scale") = 0.0, py::arg("layout") = 0, "GQA prefill (tensor-core mma on sm_80+, scalar fallback)"); }