4 Commits

Author	SHA1	Message	Date
ViperEkura	9ebaea840f	perf: cp.async K/V loads, shared sQ staging, causal skip, XOR swizzle ... - cp.async global→shared for K/V full-tile loads, eliminates 99.6% of shared-store bank conflicts (612K→2.7K per ncu) - add cp_async_16/commit/wait_all/wait_group<N> helpers in mma utils - shared sQ staging (single area, serialized per-warp load), cuts smem from (2*BC + WARPS*BR)*LD to (2*BC + BR)*LD bf16 - pre-scale Q by attention scale during Q load, removes per-tile scale multiply in softmax loop - causal tile skipping: block-level early break + warp-level skip - scalar fallback only for last partial tile - XOR swizzle (swiz_col) at 8-bf16 chunk granularity, eliminates ldmatrix bank conflicts without LD padding, LD=HEAD_DIM (zero smem waste), saves 1280 bytes/block vs HEAD_DIM+8 padding	2026-07-08 12:30:32 +08:00
ViperEkura	6adc221c10	refactor: extract shared MMA utils into gqa_mma_utils.cuh ... - Move mma16816, ld2, pk2, pkb, ldmatrix_x4/x2/x2_trans to shared header - gqa_prefill_attn_mma.cuh and gqa_decode_attn_mma.cuh both include it	2026-07-07 23:01:15 +08:00
ViperEkura	f1cc7cedce	feat: ldmatrix + smem padding for mma prefill kernel ... - replace scalar fragment loads with ldmatrix.sync.x4/x2 - add smem row-stride padding (LD = HEAD_DIM + 8) to eliminate 8-way bank conflicts from HEAD_DIM being a 32-bank multiple - switch build flag from positive to negative: -DASTRAI_NO_MMA for pre-sm_80 only; mma is the default path - vectorize scalar path smem loads with float4 ld8 - fix pure-C test configs for ld8 alignment	2026-07-06 20:55:22 +08:00
ViperEkura	ddc4bd1cf6	feat: tensor-core mma prefill with build-time dispatch ... - add register-resident flash-attention kernel using mma.sync.m16n8k16 - dispatch mma vs scalar at build time: pre-sm_80 defines -DASTRAI_NO_MMA, else defaults to mma - scalar path vectorized with float4 smem loads (ld8)	2026-07-06 20:33:24 +08:00