perf: apply cp.async, XOR swizzle, pre-scaled Q to decode MMA kernel
Decode MMA kernel previously used scalar global→shared loads with LD=HEAD_DIM+8 padding and per-tile scale multiply. This commit brings it in line with the prefill MMA kernel (which already had these optimizations): - cp.async K/V loads (bypasses registers, halves load instructions) - XOR swizzle: LD=HEAD_DIM instead of HEAD_DIM+8 (zero waste smem) - Pre-scale Q during load (removes per-tile scale multiply in softmax) - Clean up prefill MMA kernel comments (no code change) ~2x speedup on decode (0.47ms→0.24ms at seq_len=512)
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@ -8,14 +8,15 @@
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template <int HEAD_DIM>
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static void dispatch_decode(GQAParams& p) {
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#ifndef ASTRAI_NO_MMA
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constexpr int BC = 32, LD = HEAD_DIM + 8;
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constexpr int BC = 32, BR = 16, LD = HEAD_DIM; // XOR swizzle → no padding
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int G = p.q_head / p.kv_head;
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// head-packing tensor-core path needs 1 < G <= 16 (MMA M dim) and no mask;
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// everything else uses the scalar kernel
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if (!p.use_mask && G > 1 && G <= 16) {
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dim3 grid(p.kv_head, p.batch, 1);
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dim3 block(32, 1, 1);
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int smem = (2 * BC * LD + 16 * LD) * (int)sizeof(bf16);
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// sK + sV + sQ, each BC/BR * LD (single buffer for high occupancy)
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int smem = (2 * BC * LD + BR * LD) * (int)sizeof(bf16);
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cudaFuncSetAttribute(gqa_decode_attn_mma_kernel<HEAD_DIM, BC>,
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cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
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gqa_decode_attn_mma_kernel<HEAD_DIM, BC><<<grid, block, smem>>>(p);
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@ -2,7 +2,7 @@
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#include "gqa_common.cuh"
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#include "gqa_mma_utils.cuh"
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// Tensor-core decode via GQA head-packing.
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// Tensor-core decode via GQA head-packing with cp.async loads.
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//
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// Decode has q_len == 1, so S = q @ K^T is a GEMV per head — no tensor-core work
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// on its own. But GQA gives us G = q_head / kv_head query heads that all share
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@ -14,6 +14,12 @@
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// instead of different sequence positions of one head, and (2) causal masking is
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// a single scalar bound shared by every row. One warp owns one (batch, kv_head);
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// requires G <= 16.
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//
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// Optimizations:
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// - cp.async global→shared for K/V (bypasses registers, cuts instruction count)
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// - XOR swizzle (swiz_col): LD=HEAD_DIM, zero waste, no bank conflicts
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// - pre-scaled Q: Q scaled during load, softmax skips per-tile multiply
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// - single-buffer: keeps smem small for high occupancy
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template <int HEAD_DIM, int BC>
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__global__ void gqa_decode_attn_mma_kernel(GQAParams p) {
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@ -22,7 +28,8 @@ __global__ void gqa_decode_attn_mma_kernel(GQAParams p) {
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constexpr int NC8 = BC / 8; // S n-tiles (N=8 each)
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constexpr int KT2 = BC / 16; // P k-tiles (K=16 each)
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constexpr int DN8 = HEAD_DIM / 8; // O n-tiles (N=8 each)
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constexpr int LD = HEAD_DIM + 8; // padded smem row stride
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constexpr int LD = HEAD_DIM; // XOR swizzle handles bank conflicts, zero waste
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constexpr int SWIZ_MASK = (HEAD_DIM >= 64) ? 7 : (HEAD_DIM / 8 - 1);
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const int lane = threadIdx.x; // single warp
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const int gid = lane >> 2; // 0..7 → rows gid, gid+8
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@ -38,7 +45,8 @@ __global__ void gqa_decode_attn_mma_kernel(GQAParams p) {
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bf16* sV = sK + BC * LD; // [BC][LD]
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bf16* sQ = sV + BC * LD; // [BR][LD]
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// stage Q: row r == query head (q_head0 + r) at position 0 (zero-padded past G)
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// ---- stage Q into shared (pre-scaled, swizzled) ----
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bf16 scale_bf16 = __float2bfloat16(p.scale);
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for (int i = lane; i < BR * HEAD_DIM; i += 32) {
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int r = i / HEAD_DIM, d = i % HEAD_DIM;
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bf16 val = __float2bfloat16(0.0f);
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@ -46,7 +54,7 @@ __global__ void gqa_decode_attn_mma_kernel(GQAParams p) {
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int qh = q_head0 + r;
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val = p.q[(batch * p.q_head + qh) * HEAD_DIM + d]; // q_len == 1
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}
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sQ[r * LD + d] = val;
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sQ[r * LD + swiz_col(d, r, SWIZ_MASK)] = __hmul(val, scale_bf16);
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}
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__syncwarp();
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@ -56,7 +64,7 @@ __global__ void gqa_decode_attn_mma_kernel(GQAParams p) {
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int qcol_l = (lane & 16) ? 8 : 0;
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#pragma unroll
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for (int kt = 0; kt < KD; kt++)
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ldmatrix_x4(Qa[kt], &sQ[qrow_l * LD + kt * 16 + qcol_l]);
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ldmatrix_x4(Qa[kt], &sQ[qrow_l * LD + swiz_col(kt * 16 + qcol_l, qrow_l, SWIZ_MASK)]);
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float Oacc[DN8][4];
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#pragma unroll
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@ -65,21 +73,43 @@ __global__ void gqa_decode_attn_mma_kernel(GQAParams p) {
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float m0 = -FLT_MAX, m1 = -FLT_MAX, l0 = 0.0f, l1 = 0.0f;
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const int kv_base = (batch * p.kv_head + kv_head) * p.kv_len * HEAD_DIM;
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const int mask_base = batch * p.kv_len;
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const int tiles = (p.kv_len + BC - 1) / BC;
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const int has_mask = p.use_mask && p.mask;
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for (int ti = 0; ti < tiles; ti++) {
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int kv0 = ti * BC;
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// ---- load K/V tile to shared (cp.async on full tiles) ----
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bool full_tile = (kv0 + BC <= p.kv_len);
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if (full_tile) {
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constexpr int VEC = 8; // 8 bf16 = 16 bytes per cp.async
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int total = BC * HEAD_DIM;
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#pragma unroll
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for (int i = lane * VEC; i < total; i += 32 * VEC) {
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int r = i / HEAD_DIM, d = i % HEAD_DIM;
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int kc = kv0 + r;
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cp_async_16(&sK[r * LD + swiz_col(d, r, SWIZ_MASK)],
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&p.k[kv_base + kc * HEAD_DIM + d]);
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cp_async_16(&sV[r * LD + swiz_col(d, r, SWIZ_MASK)],
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&p.v[kv_base + kc * HEAD_DIM + d]);
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}
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cp_async_commit();
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cp_async_wait_all();
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} else {
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for (int i = lane; i < BC * HEAD_DIM; i += 32) {
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int r = i / HEAD_DIM, d = i % HEAD_DIM;
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int kc = kv0 + r;
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bf16 z = __float2bfloat16(0.0f);
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sK[r * LD + d] = (kc < p.kv_len) ? p.k[kv_base + kc * HEAD_DIM + d] : z;
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sV[r * LD + d] = (kc < p.kv_len) ? p.v[kv_base + kc * HEAD_DIM + d] : z;
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sK[r * LD + swiz_col(d, r, SWIZ_MASK)] =
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(kc < p.kv_len) ? p.k[kv_base + kc * HEAD_DIM + d] : z;
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sV[r * LD + swiz_col(d, r, SWIZ_MASK)] =
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(kc < p.kv_len) ? p.v[kv_base + kc * HEAD_DIM + d] : z;
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}
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}
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__syncwarp();
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// S = Q @ K^T
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// S = Q @ K^T (Q already pre-scaled, so Sacc includes scale)
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float Sacc[NC8][4];
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#pragma unroll
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for (int n8 = 0; n8 < NC8; n8++) {
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@ -89,28 +119,28 @@ __global__ void gqa_decode_attn_mma_kernel(GQAParams p) {
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#pragma unroll
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for (int kt = 0; kt < KD; kt++) {
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unsigned b[2];
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ldmatrix_x2(b, &sK[krow_l * LD + kt * 16 + kcol_h]);
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ldmatrix_x2(b, &sK[krow_l * LD + swiz_col(kt * 16 + kcol_h, krow_l, SWIZ_MASK)]);
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mma16816(Sacc[n8], Qa[kt], b, Sacc[n8]);
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}
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}
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// ---- online softmax (single query position → one causal bound per col) ----
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// ---- online softmax (Q pre-scaled → no per-tile scale multiply) ----
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float rmax0 = -FLT_MAX, rmax1 = -FLT_MAX;
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#pragma unroll
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for (int n8 = 0; n8 < NC8; n8++) {
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int cc = kv0 + n8 * 8 + 2 * tid4;
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bool bc0 = (cc >= p.kv_len) ||
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(p.use_mask && p.mask && !p.mask[batch * p.kv_len + cc]);
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(has_mask && !p.mask[mask_base + cc]);
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bool bc1 = (cc + 1 >= p.kv_len) ||
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(p.use_mask && p.mask && !p.mask[batch * p.kv_len + cc + 1]);
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(has_mask && !p.mask[mask_base + cc + 1]);
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bool cz = p.is_causal;
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int off = p.causal_offset;
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bool bad0 = bc0 || (cz && cc > off);
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bool bad1 = bc1 || (cz && (cc + 1) > off);
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float s0 = bad0 ? -FLT_MAX : Sacc[n8][0] * p.scale;
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float s1 = bad1 ? -FLT_MAX : Sacc[n8][1] * p.scale;
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float s2 = bad0 ? -FLT_MAX : Sacc[n8][2] * p.scale;
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float s3 = bad1 ? -FLT_MAX : Sacc[n8][3] * p.scale;
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float s0 = bad0 ? -FLT_MAX : Sacc[n8][0];
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float s1 = bad1 ? -FLT_MAX : Sacc[n8][1];
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float s2 = bad0 ? -FLT_MAX : Sacc[n8][2];
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float s3 = bad1 ? -FLT_MAX : Sacc[n8][3];
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Sacc[n8][0] = s0; Sacc[n8][1] = s1; Sacc[n8][2] = s2; Sacc[n8][3] = s3;
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rmax0 = fmaxf(rmax0, fmaxf(s0, s1));
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rmax1 = fmaxf(rmax1, fmaxf(s2, s3));
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@ -161,7 +191,7 @@ __global__ void gqa_decode_attn_mma_kernel(GQAParams p) {
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#pragma unroll
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for (int dn8 = 0; dn8 < DN8; dn8++) {
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unsigned b[2];
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ldmatrix_x2_trans(b, &sV[vrow_l * LD + dn8 * 8]);
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ldmatrix_x2_trans(b, &sV[vrow_l * LD + swiz_col(dn8 * 8, vrow_l, SWIZ_MASK)]);
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mma16816(Oacc[dn8], Pa, b, Oacc[dn8]);
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}
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}
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@ -11,7 +11,7 @@ static void dispatch_prefill(GQAParams& p) {
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constexpr int WARPS = 4, BC = 32, BR = 16, LD = HEAD_DIM;
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dim3 grid((p.q_len + BR * WARPS - 1) / (BR * WARPS), p.q_head, p.batch);
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dim3 block(WARPS * 32, 1, 1);
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// shared sQ: single staging area (BR*LD), not per-warp
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// sK + sV (each BC*LD) + shared sQ staging (BR*LD)
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int smem = (2 * BC * LD + BR * LD) * (int)sizeof(bf16);
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cudaFuncSetAttribute(gqa_prefill_attn_mma_kernel<HEAD_DIM, WARPS, BC>,
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cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
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@ -12,15 +12,11 @@
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// repack; row reductions fold across the 4-lane thread group. Templated on
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// <HEAD_DIM, WARPS, BC> with BC a multiple of 16.
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//
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// Optimizations vs v6 baseline: shared sQ staging (single area, serialized
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// per-warp load) → cuts smem from (2*BC + WARPS*BR)*LD to (2*BC + BR)*LD bf16,
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// raising occupancy; pre-scale Q by attention scale during Q load → removes
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// per-tile scale multiply in the softmax loop; cp.async global→shared for K/V
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// full-tile loads → eliminates shared-store bank conflicts and register staging,
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// scalar fallback only for the last partial tile; causal tile skipping (block-
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// level early break + warp-level skip); XOR swizzle (swiz_col) at 8-bf16 chunk
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// granularity → eliminates ldmatrix bank conflicts without LD padding, setting
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// LD=HEAD_DIM (zero waste).
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// Optimizations: shared sQ staging (single area, serialized per-warp load)
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// → cuts smem; pre-scale Q by attention scale during Q load; cp.async global→
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// shared for K/V; scalar fallback only for the last partial tile; causal tile
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// skipping (block-level early break + warp-level skip); XOR swizzle (swiz_col)
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// → eliminates ldmatrix bank conflicts without LD padding (LD=HEAD_DIM).
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template <int HEAD_DIM, int WARPS, int BC>
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__global__ void gqa_prefill_attn_mma_kernel(GQAParams p) {
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