refactor: rename gqa_* to attn_*, split-KV for all decode paths
- Rename all csrc/kernels/gqa_*.cuh/cu to attn_*, with _split_q / _split_kv strategy suffix and optional _mma compute suffix - Remove non-split MMA decode kernel, keep only split-KV path - Convert scalar decode fallback to split-KV (o_part/ml_part + combine) - Move combine kernel to attn_decode_split_kv.cuh (shared by both paths) - Rename GQAParams to AttentionParams - Update all C++ #include, PYBIND11, and Python extension references
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#pragma once
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// Shared MMA utilities for tensor-core GQA kernels.
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// mma.sync.m16n8k16 PTX wrappers, ldmatrix helpers, and bf16 packing.
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// mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32
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__device__ __forceinline__ void mma16816(float* d, const unsigned* a,
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const unsigned* b, const float* c) {
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asm volatile(
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"mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 "
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"{%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%10,%11,%12,%13};"
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: "=f"(d[0]), "=f"(d[1]), "=f"(d[2]), "=f"(d[3])
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: "r"(a[0]), "r"(a[1]), "r"(a[2]), "r"(a[3]), "r"(b[0]), "r"(b[1]),
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"f"(c[0]), "f"(c[1]), "f"(c[2]), "f"(c[3]));
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}
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// read two adjacent bf16 from smem as one packed .b32 (elem0 low, elem1 high)
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__device__ __forceinline__ unsigned ld2(const bf16* p) {
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return *reinterpret_cast<const unsigned*>(p);
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}
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// pack two floats into one bf16x2 as .b32
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__device__ __forceinline__ unsigned pk2(float a, float b) {
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__nv_bfloat162 v = __floats2bfloat162_rn(a, b);
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return *reinterpret_cast<unsigned*>(&v);
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}
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// pack two (non-contiguous) bf16 into one .b32
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__device__ __forceinline__ unsigned pkb(bf16 a, bf16 b) {
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__nv_bfloat162 v;
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v.x = a;
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v.y = b;
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return *reinterpret_cast<unsigned*>(&v);
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}
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// ldmatrix: cooperatively load mma fragments from smem (one instruction per
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// 16x16 / 16x8 tile) with the exact register layout mma expects — replaces the
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// scalar per-thread fragment packing, cutting shared-load instructions and bank
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// conflicts. Each lane supplies the shared address of one 8-wide row.
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__device__ __forceinline__ void ldmatrix_x4(unsigned* r, const bf16* p) {
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unsigned a = __cvta_generic_to_shared(p);
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asm volatile("ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0,%1,%2,%3}, [%4];"
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: "=r"(r[0]), "=r"(r[1]), "=r"(r[2]), "=r"(r[3])
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: "r"(a));
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}
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__device__ __forceinline__ void ldmatrix_x2(unsigned* r, const bf16* p) {
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unsigned a = __cvta_generic_to_shared(p);
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asm volatile("ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0,%1}, [%2];"
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: "=r"(r[0]), "=r"(r[1])
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: "r"(a));
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}
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__device__ __forceinline__ void ldmatrix_x2_trans(unsigned* r, const bf16* p) {
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unsigned a = __cvta_generic_to_shared(p);
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asm volatile("ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {%0,%1}, [%2];"
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: "=r"(r[0]), "=r"(r[1])
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: "r"(a));
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}
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// XOR swizzle for shared-memory column at 8-bf16 chunk granularity.
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// Eliminates ldmatrix bank conflicts without LD padding: consecutive rows
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// land in distinct bank groups. swiz_col(d, r, mask) = ((d>>3)^(r&mask))<<3 | (d&7).
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// mask must cover log2(HEAD_DIM/8) chunk bits but stay within LD: use 7 for
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// HEAD_DIM>=64 (8+ chunks), 3 for HEAD_DIM=32 (4 chunks). Default 7 keeps
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// existing HEAD_DIM>=64 call sites working unchanged.
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__device__ __forceinline__ int swiz_col(int d, int r, int mask = 7) {
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return ((d >> 3) ^ (r & mask)) << 3 | (d & 7);
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}
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// cp.async: copy 16 bytes (8 bf16) from global to shared memory directly,
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// bypassing registers. Eliminates shared-store bank conflicts and cuts
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// load-loop instruction count in half (1 cp.async vs 1 LDG + 1 STS).
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// Requires sm_80+.
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__device__ __forceinline__ void cp_async_16(bf16* smem_ptr, const void* gmem_ptr) {
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unsigned smem_addr = __cvta_generic_to_shared(smem_ptr);
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asm volatile("cp.async.ca.shared.global [%0], [%1], 16;"
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:: "r"(smem_addr), "l"(gmem_ptr));
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}
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// Predicated cp.async: copy 16 bytes when `pred`, otherwise zero-fill the
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// destination (src-size operand = 0 → no bytes read from src, so an
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// out-of-bounds src address is never dereferenced). Lets full and partial
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// tiles share one uniform async load path — no scalar fallback branch.
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__device__ __forceinline__ void cp_async_16_pred(bf16* smem_ptr,
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const void* gmem_ptr,
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bool pred) {
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unsigned smem_addr = __cvta_generic_to_shared(smem_ptr);
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int src_size = pred ? 16 : 0;
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asm volatile("cp.async.ca.shared.global [%0], [%1], 16, %2;"
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:: "r"(smem_addr), "l"(gmem_ptr), "r"(src_size));
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}
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__device__ __forceinline__ void cp_async_commit() {
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asm volatile("cp.async.commit_group;");
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}
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__device__ __forceinline__ void cp_async_wait_all() {
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asm volatile("cp.async.wait_all;");
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}
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// Wait until at most N commit groups are still in flight. Used for
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// double-buffered pipelining: wait_group<1> lets the next tile's cp.async
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// continue while ensuring the current tile's data is ready.
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template <int N>
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__device__ __forceinline__ void cp_async_wait_group() {
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asm volatile("cp.async.wait_group %0;" :: "n"(N));
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}
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// ---------------------------------------------------------------------------
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// Shared MMA compute functions — used by both decode and prefill MMA kernels.
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// Extracted because S=Q@K^T, online softmax, and P@V are structurally identical
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// between the two kernels; only the per-row causal/mask bounds differ.
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// ---------------------------------------------------------------------------
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// S = Q @ K^T (Qa pre-loaded and pre-scaled by the caller).
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// LD and SWIZ_MASK are constexpr in the calling kernel — passing them as
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// runtime ints lets the compiler fold them while keeping the signature clean.
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template <int KD, int NC8>
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__device__ inline void mma_compute_scores(
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const unsigned Qa[KD][4],
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const bf16* __restrict__ sK,
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int LD, int SWIZ_MASK, int lane,
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float Sacc[NC8][4])
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{
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#pragma unroll
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for (int n8 = 0; n8 < NC8; n8++) {
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Sacc[n8][0] = Sacc[n8][1] = Sacc[n8][2] = Sacc[n8][3] = 0.0f;
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int krow_l = n8 * 8 + (lane & 7);
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int kcol_h = (lane & 8) ? 8 : 0;
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#pragma unroll
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for (int kt = 0; kt < KD; kt++) {
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unsigned b[2];
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ldmatrix_x2(b, &sK[krow_l * LD + swiz_col(kt * 16 + kcol_h, krow_l, SWIZ_MASK)]);
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mma16816(Sacc[n8], Qa[kt], b, Sacc[n8]);
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}
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}
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}
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// Online softmax + Oacc rescale for one K/V tile. maxc0/maxc1 are the per-row
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// KV column bounds — prefill passes per-query-row causal limits while decode
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// passes the same value for both rows (q_len==1). Sacc is consumed in place
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// (replaced by P = exp(S - nm) for the subsequent P@V step).
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template <int NC8, int DN8>
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__device__ inline void mma_softmax_tile(
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int kv0,
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int maxc0, int maxc1,
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int mask_base,
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const bool* __restrict__ mask,
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bool has_mask,
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float Sacc[NC8][4],
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float Oacc[DN8][4],
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float& m0, float& m1,
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float& l0, float& l1,
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int lane)
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{
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int tid4 = lane & 3;
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float rmax0 = -FLT_MAX, rmax1 = -FLT_MAX;
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#pragma unroll
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for (int n8 = 0; n8 < NC8; n8++) {
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int cc = kv0 + n8 * 8 + 2 * tid4;
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int c1 = cc + 1;
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bool b0 = (cc >= maxc0) || (has_mask && !mask[mask_base + cc]);
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bool b1 = (c1 >= maxc0) || (has_mask && !mask[mask_base + c1]);
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bool b2 = (cc >= maxc1) || (has_mask && !mask[mask_base + cc]);
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bool b3 = (c1 >= maxc1) || (has_mask && !mask[mask_base + c1]);
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float s0 = b0 ? -FLT_MAX : Sacc[n8][0];
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float s1 = b1 ? -FLT_MAX : Sacc[n8][1];
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float s2 = b2 ? -FLT_MAX : Sacc[n8][2];
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float s3 = b3 ? -FLT_MAX : Sacc[n8][3];
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Sacc[n8][0] = s0; Sacc[n8][1] = s1;
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Sacc[n8][2] = s2; Sacc[n8][3] = s3;
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rmax0 = fmaxf(rmax0, fmaxf(s0, s1));
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rmax1 = fmaxf(rmax1, fmaxf(s2, s3));
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}
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rmax0 = fmaxf(rmax0, __shfl_xor_sync(0xFFFFFFFF, rmax0, 1));
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rmax0 = fmaxf(rmax0, __shfl_xor_sync(0xFFFFFFFF, rmax0, 2));
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rmax1 = fmaxf(rmax1, __shfl_xor_sync(0xFFFFFFFF, rmax1, 1));
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rmax1 = fmaxf(rmax1, __shfl_xor_sync(0xFFFFFFFF, rmax1, 2));
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float nm0 = fmaxf(m0, rmax0), nm1 = fmaxf(m1, rmax1);
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float corr0 = (nm0 == -FLT_MAX) ? 1.0f : __expf(m0 - nm0);
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float corr1 = (nm1 == -FLT_MAX) ? 1.0f : __expf(m1 - nm1);
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float rsum0 = 0.0f, rsum1 = 0.0f;
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#pragma unroll
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for (int n8 = 0; n8 < NC8; n8++) {
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float p0 = (Sacc[n8][0] == -FLT_MAX) ? 0.0f : __expf(Sacc[n8][0] - nm0);
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float p1 = (Sacc[n8][1] == -FLT_MAX) ? 0.0f : __expf(Sacc[n8][1] - nm0);
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float p2 = (Sacc[n8][2] == -FLT_MAX) ? 0.0f : __expf(Sacc[n8][2] - nm1);
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float p3 = (Sacc[n8][3] == -FLT_MAX) ? 0.0f : __expf(Sacc[n8][3] - nm1);
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Sacc[n8][0] = p0; Sacc[n8][1] = p1;
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Sacc[n8][2] = p2; Sacc[n8][3] = p3;
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rsum0 += p0 + p1;
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rsum1 += p2 + p3;
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}
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rsum0 += __shfl_xor_sync(0xFFFFFFFF, rsum0, 1);
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rsum0 += __shfl_xor_sync(0xFFFFFFFF, rsum0, 2);
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rsum1 += __shfl_xor_sync(0xFFFFFFFF, rsum1, 1);
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rsum1 += __shfl_xor_sync(0xFFFFFFFF, rsum1, 2);
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l0 = l0 * corr0 + rsum0;
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l1 = l1 * corr1 + rsum1;
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m0 = nm0; m1 = nm1;
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#pragma unroll
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for (int j = 0; j < DN8; j++) {
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Oacc[j][0] *= corr0; Oacc[j][1] *= corr0;
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Oacc[j][2] *= corr1; Oacc[j][3] *= corr1;
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}
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}
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// O += P @ V (Sacc must contain P = attention weights after softmax).
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template <int DN8, int KT2>
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__device__ inline void mma_pv_accumulate(
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float Sacc[][4],
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const bf16* __restrict__ sV,
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int LD, int SWIZ_MASK, int lane,
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float Oacc[DN8][4])
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{
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#pragma unroll
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for (int kt2 = 0; kt2 < KT2; kt2++) {
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unsigned Pa[4];
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Pa[0] = pk2(Sacc[kt2 * 2][0], Sacc[kt2 * 2][1]);
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Pa[1] = pk2(Sacc[kt2 * 2][2], Sacc[kt2 * 2][3]);
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Pa[2] = pk2(Sacc[kt2 * 2 + 1][0], Sacc[kt2 * 2 + 1][1]);
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Pa[3] = pk2(Sacc[kt2 * 2 + 1][2], Sacc[kt2 * 2 + 1][3]);
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int vrow_l = kt2 * 16 + (lane & 15);
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#pragma unroll
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for (int dn8 = 0; dn8 < DN8; dn8++) {
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unsigned b[2];
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ldmatrix_x2_trans(b, &sV[vrow_l * LD + swiz_col(dn8 * 8, vrow_l, SWIZ_MASK)]);
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mma16816(Oacc[dn8], Pa, b, Oacc[dn8]);
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}
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}
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}
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