feat: split kernel defs from bindings, add prefill tiled kernel and pure C tests
- Split .cuh/.cu for gqa_decode_attn and gqa_prefill_attn - gqa_prefill_attn: tiled shared-memory K/V, fused load, compute-opt, mask support - Add pure C tests under csrc/tests/ for fast nvcc-only iteration - Update .gitignore for build artifacts
This commit is contained in:
@@ -1,86 +1,8 @@
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// per-KV-head block, K shared in smem, each thread handles hd/32 elements
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#include <cuda_bf16.h>
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#include <cuda_runtime.h>
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#include <cmath>
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#include <cfloat>
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// torch binding for gqa_decode_attn
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// kernel defined in gqa_decode_attn.cuh
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#include "gqa_decode_attn.cuh"
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#include <torch/extension.h>
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using bf16 = __nv_bfloat16;
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constexpr int CHUNK = 64;
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__inline__ __device__ float warp_reduce_sum(float val) {
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for (int offset = 16; offset > 0; offset >>= 1)
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val += __shfl_xor_sync(0xFFFFFFFF, val, offset);
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return val;
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}
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__global__ void gqa_decode_attn_kernel(
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const bf16* __restrict__ q_ptr,
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const bf16* __restrict__ k_ptr,
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const bf16* __restrict__ v_ptr,
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const bool* __restrict__ mask_ptr,
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bf16* __restrict__ out_ptr,
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int B, int n_heads, int n_kv_heads, int seq_len, int hd
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) {
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int batch = blockIdx.x / n_kv_heads;
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int kv_head = blockIdx.x % n_kv_heads;
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int group_size = blockDim.y;
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int q_head = kv_head * group_size + threadIdx.y;
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int lane = threadIdx.x;
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int hd_per_thread = hd / 32;
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float q_reg[8];
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int q_off = ((batch * n_heads + q_head) * 1) * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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q_reg[i] = __bfloat162float(q_ptr[q_off + i]);
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int kv_base = ((batch * n_kv_heads + kv_head) * seq_len) * hd;
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int mask_base = batch * seq_len;
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float m = -FLT_MAX, d = 0.0f, acc_reg[8] = {0.0f};
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float scale = rsqrtf((float)hd);
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extern __shared__ __align__(16) bf16 k_smem[];
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for (int chunk_start = 0; chunk_start < seq_len; chunk_start += CHUNK) {
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int this_chunk = min(CHUNK, seq_len - chunk_start);
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int total = this_chunk * hd;
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for (int i = threadIdx.y * 32 + lane; i < total; i += blockDim.x * blockDim.y)
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k_smem[i] = k_ptr[kv_base + chunk_start * hd + i];
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__syncthreads();
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for (int s = 0; s < this_chunk; s++) {
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float partial = 0.0f;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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partial += q_reg[i] * __bfloat162float(k_smem[s * hd + lane * hd_per_thread + i]);
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partial = warp_reduce_sum(partial) * scale;
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if (!mask_ptr[mask_base + chunk_start + s]) partial = -FLT_MAX;
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float new_m = fmaxf(m, partial);
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float alpha = expf(m - new_m);
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float beta = expf(partial - new_m);
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d = d * alpha + beta;
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int v_off = kv_base + (chunk_start + s) * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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acc_reg[i] = acc_reg[i] * alpha + __bfloat162float(v_ptr[v_off + i]) * beta;
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m = new_m;
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}
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__syncthreads();
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}
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int out_off = ((batch * n_heads + q_head) * 1) * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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out_ptr[out_off + i] = __float2bfloat16(acc_reg[i] / d);
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}
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torch::Tensor gqa_decode_attn(
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torch::Tensor q, torch::Tensor k, torch::Tensor v, torch::Tensor mask
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) {
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@@ -97,7 +19,7 @@ torch::Tensor gqa_decode_attn(
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int group_size = n_heads / n_kv;
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auto out = torch::empty_like(q);
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size_t smem = CHUNK * hd * sizeof(bf16); // K chunk
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size_t smem = DC_CHUNK * hd * sizeof(bf16);
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dim3 block(32, group_size);
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dim3 grid(B * n_kv);
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@@ -0,0 +1,78 @@
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// gqa_decode_attn.cuh — header-only decode kernel
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#pragma once
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#include <cuda_bf16.h>
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#include <cuda_runtime.h>
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#include <cfloat>
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#include <algorithm>
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using std::min;
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using bf16 = __nv_bfloat16;
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constexpr int DC_CHUNK = 64;
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__device__ inline float warp_reduce_sum(float val) {
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for (int offset = 16; offset > 0; offset >>= 1)
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val += __shfl_xor_sync(0xFFFFFFFF, val, offset);
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return val;
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}
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__global__ void gqa_decode_attn_kernel(
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const bf16* __restrict__ q_ptr,
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const bf16* __restrict__ k_ptr,
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const bf16* __restrict__ v_ptr,
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const bool* __restrict__ mask_ptr,
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bf16* __restrict__ out_ptr,
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int B, int n_heads, int n_kv_heads, int seq_len, int hd
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) {
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int batch = blockIdx.x / n_kv_heads;
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int kv_head = blockIdx.x % n_kv_heads;
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int group_size = blockDim.y;
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int q_head = kv_head * group_size + threadIdx.y;
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int lane = threadIdx.x;
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int hd_per_thread = hd / 32;
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float q_reg[8];
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int q_off = ((batch * n_heads + q_head) * 1) * hd + lane * hd_per_thread;
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for (int i = 0; i < hd_per_thread; i++)
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q_reg[i] = __bfloat162float(q_ptr[q_off + i]);
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int kv_base = ((batch * n_kv_heads + kv_head) * seq_len) * hd;
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int mask_base = batch * seq_len;
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float m = -FLT_MAX, d = 0.0f, acc_reg[8] = {0.0f};
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float scale = rsqrtf((float)hd);
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extern __shared__ __align__(16) bf16 k_smem[];
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for (int chunk_start = 0; chunk_start < seq_len; chunk_start += DC_CHUNK) {
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int this_chunk = min(DC_CHUNK, seq_len - chunk_start);
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int total = this_chunk * hd;
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for (int i = threadIdx.y * 32 + lane; i < total; i += blockDim.x * blockDim.y)
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k_smem[i] = k_ptr[kv_base + chunk_start * hd + i];
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__syncthreads();
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for (int s = 0; s < this_chunk; s++) {
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float partial = 0.0f;
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for (int i = 0; i < hd_per_thread; i++)
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partial += q_reg[i] * __bfloat162float(k_smem[s * hd + lane * hd_per_thread + i]);
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partial = warp_reduce_sum(partial) * scale;
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if (!mask_ptr[mask_base + chunk_start + s]) partial = -FLT_MAX;
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float new_m = fmaxf(m, partial);
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float alpha = expf(m - new_m);
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float beta = expf(partial - new_m);
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d = d * alpha + beta;
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int v_off = kv_base + (chunk_start + s) * hd + lane * hd_per_thread;
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for (int i = 0; i < hd_per_thread; i++)
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acc_reg[i] = acc_reg[i] * alpha + __bfloat162float(v_ptr[v_off + i]) * beta;
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m = new_m;
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}
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__syncthreads();
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}
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int out_off = ((batch * n_heads + q_head) * 1) * hd + lane * hd_per_thread;
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for (int i = 0; i < hd_per_thread; i++)
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out_ptr[out_off + i] = __float2bfloat16(acc_reg[i] / d);
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}
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@@ -1,79 +1,8 @@
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#include <cuda_bf16.h>
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#include <cuda_runtime.h>
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#include <cmath>
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#include <cfloat>
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// torch binding for gqa_prefill_attn
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// kernel defined in gqa_prefill_attn.cuh
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#include "gqa_prefill_attn.cuh"
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#include <torch/extension.h>
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using bf16 = __nv_bfloat16;
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__inline__ __device__ float warp_reduce_sum(float val) {
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for (int offset = 16; offset > 0; offset >>= 1)
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val += __shfl_xor_sync(0xFFFFFFFF, val, offset);
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return val;
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}
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__global__ void gqa_prefill_attn_kernel(
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const bf16* __restrict__ q_ptr,
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const bf16* __restrict__ k_ptr,
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const bf16* __restrict__ v_ptr,
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const bool* __restrict__ mask_ptr,
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bf16* __restrict__ out_ptr,
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int B, int n_heads, int n_kv_heads, int q_len, int kv_len, int hd,
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int use_mask, int is_causal, int causal_offset
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) {
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int flat_id = blockIdx.x;
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int pos = flat_id % q_len;
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flat_id /= q_len;
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int q_head = flat_id % n_heads;
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int batch = flat_id / n_heads;
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int kv_head = q_head / (n_heads / n_kv_heads);
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int lane = threadIdx.x;
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int hd_per_thread = hd / 32;
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// each thread handles hd/32 elements of Q
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float q_reg[8];
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int q_off = ((batch * n_heads + q_head) * q_len + pos) * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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q_reg[i] = __bfloat162float(q_ptr[q_off + i]);
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int kv_base = ((batch * n_kv_heads + kv_head) * kv_len) * hd;
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int limit = is_causal ? min(pos + causal_offset + 1, kv_len) : kv_len;
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float m = -FLT_MAX, d = 0.0f, acc_reg[8] = {0.0f};
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float scale = rsqrtf((float)hd);
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int mask_stride = q_len * kv_len;
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int mask_off = batch * mask_stride + pos * kv_len;
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for (int s = 0; s < limit; s++) {
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float partial = 0.0f;
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int k_off = kv_base + s * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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partial += q_reg[i] * __bfloat162float(k_ptr[k_off + i]);
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partial = warp_reduce_sum(partial) * scale;
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if (use_mask && !mask_ptr[mask_off + s]) partial = -FLT_MAX;
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float new_m = fmaxf(m, partial);
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float alpha = expf(m - new_m);
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float beta = expf(partial - new_m);
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d = d * alpha + beta;
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int v_off = kv_base + s * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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acc_reg[i] = acc_reg[i] * alpha + __bfloat162float(v_ptr[v_off + i]) * beta;
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m = new_m;
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}
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int out_off = ((batch * n_heads + q_head) * q_len + pos) * hd + lane * hd_per_thread;
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#pragma unroll
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for (int i = 0; i < hd_per_thread; i++)
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out_ptr[out_off + i] = __float2bfloat16(acc_reg[i] / d);
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}
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torch::Tensor gqa_prefill_attn(
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torch::Tensor q, torch::Tensor k, torch::Tensor v,
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c10::optional<torch::Tensor> mask,
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@@ -85,34 +14,34 @@ torch::Tensor gqa_prefill_attn(
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TORCH_CHECK(k.dtype() == torch::kBFloat16);
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TORCH_CHECK(v.dtype() == torch::kBFloat16);
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int B = q.size(0), n_heads = q.size(1), q_len = q.size(2), hd = q.size(3);
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int n_kv = k.size(1), kv_len = k.size(2);
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TORCH_CHECK(hd % 32 == 0, "head_dim must be multiple of 32");
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int B = q.size(0), Hq = q.size(1), q_len = q.size(2), D = q.size(3);
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int Hk = k.size(1), kv_len = k.size(2);
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TORCH_CHECK(D % 32 == 0, "head_dim must be multiple of 32");
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bool use_mask = mask.has_value();
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const bool* mask_ptr = nullptr;
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if (use_mask) {
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TORCH_CHECK(mask.value().dtype() == torch::kBool);
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TORCH_CHECK(mask.value().dim() == 2);
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TORCH_CHECK(mask.value().size(0) == B);
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TORCH_CHECK(mask.value().size(1) == kv_len);
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mask_ptr = mask.value().data_ptr<bool>();
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}
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auto out = torch::empty_like(q);
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auto O = torch::empty_like(q);
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dim3 block(32);
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dim3 grid(B * n_heads * q_len);
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dim3 grid((q_len + Br - 1) / Br, Hq, B);
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dim3 block(32, Br, 1);
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size_t smem = 2 * Bc * D * sizeof(bf16);
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gqa_prefill_attn_kernel<<<grid, block>>>(
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reinterpret_cast<const bf16*>(q.data_ptr()),
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reinterpret_cast<const bf16*>(k.data_ptr()),
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reinterpret_cast<const bf16*>(v.data_ptr()),
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mask_ptr,
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reinterpret_cast<bf16*>(out.data_ptr()),
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B, n_heads, n_kv, q_len, kv_len, hd,
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(int)use_mask, (int)is_causal, (int)causal_offset
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gqa_prefill_attn_kernel<<<grid, block, smem>>>(
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(const bf16*)q.data_ptr(), (const bf16*)k.data_ptr(),
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(const bf16*)v.data_ptr(), mask_ptr, (bf16*)O.data_ptr(),
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B, Hq, Hk, q_len, kv_len, D, (int)is_causal, (int)causal_offset, (int)use_mask
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);
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return out;
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return O;
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}
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PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
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m.def("gqa_prefill_attn", &gqa_prefill_attn, "GQA prefill attention (naive)");
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m.def("gqa_prefill_attn", &gqa_prefill_attn, "GQA prefill v3 (compute-opt)");
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}
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@@ -0,0 +1,100 @@
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// gqa_prefill_attn.cuh — header-only kernel definition (no torch dependency)
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#pragma once
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#include <cuda_bf16.h>
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#include <cuda_runtime.h>
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#include <cfloat>
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using bf16 = __nv_bfloat16;
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static constexpr int Br = 32;
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static constexpr int Bc = 64;
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__device__ inline float warp_sum(float v) {
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for (int off = 16; off > 0; off >>= 1)
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v += __shfl_xor_sync(0xffffffff, v, off);
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return v;
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}
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__global__ void gqa_prefill_attn_kernel(
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const bf16* __restrict__ Q, const bf16* __restrict__ K,
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const bf16* __restrict__ V, const bool* __restrict__ mask,
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bf16* __restrict__ O,
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int B, int Hq, int Hk, int q_len, int kv_len, int D,
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int is_causal, int causal_offset, int use_mask
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) {
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int q_tile = blockIdx.x;
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int q_head = blockIdx.y;
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int batch = blockIdx.z;
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int q_row = q_tile * Br + threadIdx.y;
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int d_part = threadIdx.x;
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int dpw = D >> 5;
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int kv_head = q_head / (Hq / Hk);
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float qs[8] = {0};
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if (q_row < q_len) {
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float sc = rsqrtf((float)D);
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int q_off = (((batch * Hq + q_head) * q_len + q_row) * D) + d_part * dpw;
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for (int i = 0; i < dpw; i++)
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qs[i] = __bfloat162float(Q[q_off + i]) * sc;
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}
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int kv_base = ((batch * Hk + kv_head) * kv_len) * D;
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extern __shared__ __align__(16) bf16 smem[];
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bf16* sK = smem;
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bf16* sV = smem + Bc * D;
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float m = -FLT_MAX, l = 0.0f, acc[8] = {0};
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int tiles = (kv_len + Bc - 1) / Bc;
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int tt = blockDim.x * blockDim.y;
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for (int ti = 0; ti < tiles; ti++) {
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int kv0 = ti * Bc;
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int tlen = min(Bc, kv_len - kv0);
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for (int i = threadIdx.y * blockDim.x + threadIdx.x;
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i < tlen * D; i += tt) {
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int r = i / D, c = i % D, idx = r * D + c;
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int g_off = kv_base + (kv0 + r) * D + c;
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sK[idx] = K[g_off];
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sV[idx] = V[g_off];
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}
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__syncthreads();
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int lim = tlen;
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if (is_causal && q_row < q_len) {
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int ep = q_row + causal_offset + 1;
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if (kv0 >= ep) lim = 0;
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else if (kv0 + tlen > ep) lim = ep - kv0;
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}
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for (int s = 0; s < lim; s++) {
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float dot = 0.0f;
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for (int i = 0; i < dpw; i++)
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dot += qs[i] * __bfloat162float(sK[s * D + d_part * dpw + i]);
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dot = warp_sum(dot);
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|
||||
if (use_mask && !mask[batch * q_len * kv_len + q_row * kv_len + kv0 + s])
|
||||
dot = -FLT_MAX;
|
||||
|
||||
float nm = fmaxf(m, dot);
|
||||
float al = expf(m - nm);
|
||||
float be = expf(dot - nm);
|
||||
l = l * al + be;
|
||||
|
||||
for (int i = 0; i < dpw; i++)
|
||||
acc[i] = acc[i] * al + __bfloat162float(sV[s * D + d_part * dpw + i]) * be;
|
||||
m = nm;
|
||||
}
|
||||
__syncthreads();
|
||||
}
|
||||
|
||||
if (q_row < q_len) {
|
||||
int o_off = (((batch * Hq + q_head) * q_len + q_row) * D) + d_part * dpw;
|
||||
float rl = (l > 1e-10f) ? (1.0f / l) : 0.0f;
|
||||
for (int i = 0; i < dpw; i++)
|
||||
O[o_off + i] = __float2bfloat16(acc[i] * rl);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user