perf: increase decode split-K parallelism for short sequences
- Remove tiles_total/8 min-work cap that limited splits for small workloads - Simplify decode_num_splits to only use base_blocks and tiles_total - Short sequences now generate more blocks, improving SM utilization
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@ -27,6 +27,7 @@ NVCC_FLAGS = [
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"--use_fast_math",
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"--ptxas-options=-O3,-v",
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"--extra-device-vectorization",
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"--threads=8",
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]
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@ -5,25 +5,18 @@
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#include "attn_decode_split_kv_mma.cuh"
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#endif
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// Decode has only batch*kv_head independent tasks; without split-K the grid is
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// tiny (e.g. 16 blocks) and leaves most SMs idle. Pick the smallest split count
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// that fills the device (~2 blocks/SM), capped by the tile count, min work per
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// split (at least 8 tiles), and 32.
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static int decode_num_splits(const AttentionParams<bf16>& p, int tiles_total) {
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static int decode_num_splits(int base_blocks, int tiles_total) {
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int sm_count = 0;
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cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, 0);
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int base_blocks = p.kv_head * p.batch;
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int desired = 2 * (sm_count > 0 ? sm_count : 64);
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int n = (desired + base_blocks - 1) / base_blocks;
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int max_by_work = tiles_total / 8;
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return std::max(1, std::min({n, tiles_total, 32, max_by_work}));
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int n = (2 * sm_count + base_blocks - 1) / base_blocks;
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return std::max(1, std::min(n, std::min(tiles_total, 32)));
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}
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// Scalar fallback: one warp per query head, split-KV across grid.z.
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static void launch_scalar_decode(AttentionParams<bf16>& p) {
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int group_size = p.q_head / p.kv_head;
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int chunks_total = (p.kv_len + DC_CHUNK - 1) / DC_CHUNK;
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p.num_splits = decode_num_splits(p, chunks_total);
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p.num_splits = decode_num_splits(p.batch * p.kv_head, chunks_total);
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auto fopt = torch::TensorOptions().dtype(torch::kFloat32).device(torch::kCUDA);
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auto o_part = torch::empty({p.batch, p.q_head, p.num_splits, p.head_dim}, fopt);
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@ -46,7 +39,7 @@ static bool decode_use_mma(const AttentionParams<bf16>& p) {
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template <int HEAD_DIM, int BC>
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static void launch_mma_decode(AttentionParams<bf16>& p) {
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int tiles_total = (p.kv_len + BC - 1) / BC;
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p.num_splits = decode_num_splits(p, tiles_total);
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p.num_splits = decode_num_splits(p.batch * p.kv_head, tiles_total);
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auto fopt = torch::TensorOptions().dtype(torch::kFloat32).device(torch::kCUDA);
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auto o_part = torch::empty({p.batch, p.q_head, p.num_splits, p.head_dim}, fopt);
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@ -28,14 +28,11 @@ struct DecodeScratch {
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float* ml_part = nullptr;
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};
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static int decode_num_splits(const AttentionParams<bf16>& p, int tiles_total) {
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static int decode_num_splits(int base_blocks, int tiles_total) {
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int sm_count = 0;
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cudaDeviceGetAttribute(&sm_count, cudaDevAttrMultiProcessorCount, 0);
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int base_blocks = p.kv_head * p.batch;
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int desired = 2 * (sm_count > 0 ? sm_count : 64);
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int n = (desired + base_blocks - 1) / base_blocks;
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int max_by_work = tiles_total / 8;
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return max(1, min(min(min(n, tiles_total), 32), max_by_work));
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int n = (2 * sm_count + base_blocks - 1) / base_blocks;
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return std::max(1, std::min(n, std::min(tiles_total, 32)));
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}
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// Launch the production decode path (tensor-core head-packing MMA on sm_80+,
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@ -49,7 +46,7 @@ static bool decode_use_mma(const AttentionParams<bf16>& p) {
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template <int HEAD_DIM, int BC>
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static void launch_mma_decode(AttentionParams<bf16>& p, DecodeScratch& sc) {
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int tiles_total = (p.kv_len + BC - 1) / BC;
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p.num_splits = decode_num_splits(p, tiles_total);
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p.num_splits = decode_num_splits(p.batch * p.kv_head, tiles_total);
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p.o_part = sc.o_part;
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p.ml_part = sc.ml_part;
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@ -62,7 +59,7 @@ static void launch_mma_decode(AttentionParams<bf16>& p, DecodeScratch& sc) {
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static void launch_scalar_decode(AttentionParams<bf16>& p, DecodeScratch& sc) {
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int gs = p.q_head / p.kv_head;
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int chunks_total = (p.kv_len + DC_CHUNK - 1) / DC_CHUNK;
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p.num_splits = decode_num_splits(p, chunks_total);
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p.num_splits = decode_num_splits(p.batch * p.kv_head, chunks_total);
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p.o_part = sc.o_part;
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p.ml_part = sc.ml_part;
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