perf: accelerate FP8 backward with fused fast kernel

- route dX/dW through the fused 128x64 fast kernel via contiguous transposes
- drop the legacy 64x64 kernel, cutting dX 1.55->0.38 ms and dW 1.28->0.26 ms
- sync all threads after cp.async.wait_group to fix sporadic NaN in large GEMMs
- add fp8_mm_prequant_fp8 custom op for FP8-in/FP8-out GEMM

astrai/extension/ops/fp8.py

@@ -47,6 +47,58 @@ def _fp8_mm_cpu(a, b, sx, sw):
     return torch.mm(a.float(), b.float().t()).to(torch.bfloat16)
 
 
+@custom_op("custom::fp8_mm_prequant", mutates_args=())
+def fp8_mm_prequant(
+    a: torch.Tensor, b: torch.Tensor, scale: torch.Tensor
+) -> torch.Tensor:
+    """Pre-quantized FP8 inputs, fused FP8 GEMM, FP32 accumulation, BF16 out."""
+
+
+@fp8_mm_prequant.register_fake
+def _fp8_mm_prequant_fake(a, b, scale):
+    return torch.empty((a.size(0), b.size(0)), device=a.device, dtype=torch.bfloat16)
+
+
+@fp8_mm_prequant.register_kernel("cuda")
+def _fp8_mm_prequant_cuda(a, b, scale):
+    if not (a.dtype == torch.float8_e4m3fn and b.dtype == torch.float8_e4m3fn):
+        raise TypeError(
+            f"pre-quantized FP8 GEMM requires fp8 inputs, got {a.dtype}/{b.dtype}"
+        )
+    return _mod().fp8_mm_prequant(a, b, scale)
+
+
+@fp8_mm_prequant.register_kernel("cpu")
+def _fp8_mm_prequant_cpu(a, b, scale):
+    return (a.float() @ b.float().t() * scale).to(torch.bfloat16)
+
+
+@custom_op("custom::fp8_mm_prequant_fp8", mutates_args=())
+def fp8_mm_prequant_fp8(
+    a: torch.Tensor, b: torch.Tensor, scale: torch.Tensor, out_scale: torch.Tensor
+) -> torch.Tensor:
+    """FP8 inputs and FP8 output: fused FP8 GEMM with FP32 accumulation."""
+
+
+@fp8_mm_prequant_fp8.register_fake
+def _fp8_mm_prequant_fp8_fake(a, b, scale, out_scale):
+    return torch.empty((a.size(0), b.size(0)), device=a.device, dtype=a.dtype)
+
+
+@fp8_mm_prequant_fp8.register_kernel("cuda")
+def _fp8_mm_prequant_fp8_cuda(a, b, scale, out_scale):
+    if not (a.dtype == torch.float8_e4m3fn and b.dtype == torch.float8_e4m3fn):
+        raise TypeError(
+            f"pre-quantized FP8 GEMM requires fp8 inputs, got {a.dtype}/{b.dtype}"
+        )
+    return _mod().fp8_mm_prequant_fp8(a, b, scale, out_scale)
+
+
+@fp8_mm_prequant_fp8.register_kernel("cpu")
+def _fp8_mm_prequant_fp8_cpu(a, b, scale, out_scale):
+    return (a.float() @ b.float().t() * scale * out_scale).to(torch.float8_e4m3fn)
+
+
 def linear_forward_scaled(x, w, bias, sx, sw, sx_inv, sw_inv, amax_x, amax_w):
     """Quantize BF16 inputs to FP8, accumulate in FP32, and return BF16.
 

csrc/kernels/fp8_mm.cu

@@ -11,26 +11,19 @@
 
 namespace {
 
-constexpr int kMmaM = 16;
-constexpr int kMmaN = 8;
 constexpr int kMmaK = 32;
-constexpr int kBlockM = 32;
-constexpr int kBlockN = 32;
 constexpr int kWarps = 8;
-constexpr int kForwardBlockM = 64;
+// Fast forward path: 128x64 CTA, 64x16 warp tile, 2-stage pipeline, dynamic
-constexpr int kForwardBlockN = 64;
+// shared memory. Mirrors the CUTLASS 58_ada_fp8_gemm threadblock geometry
-
+// while keeping the fused BF16->FP8 quantize path. The FP8 tile overwrites
-__device__ __forceinline__ unsigned pack_fp8x4_scalar(float x0, float x1,
+// the BF16 staging area in place. L20 opts in to only 101376 B shared per
-                                                       float x2, float x3) {
+// block; K=32 keeps the footprint at 24576 B so four CTAs/SM stay resident.
-    __nv_fp8_e4m3 q0(x0);
+constexpr int kFastBlockM = 128;
-    __nv_fp8_e4m3 q1(x1);
+constexpr int kFastBlockN = 64;
-    __nv_fp8_e4m3 q2(x2);
+constexpr int kFastK = 32;
-    __nv_fp8_e4m3 q3(x3);
+constexpr int kFastStages = 2;
-    return static_cast<unsigned>(q0.__x) |
+constexpr int kFastSmemBytes =
-           (static_cast<unsigned>(q1.__x) << 8) |
+    kFastStages * (kFastBlockM * kFastK * 2 + kFastBlockN * kFastK * 2);
-           (static_cast<unsigned>(q2.__x) << 16) |
-           (static_cast<unsigned>(q3.__x) << 24);
-}
 
 __device__ __forceinline__ unsigned pack_fp8x4_vector(float x0, float x1,
                                                        float x2, float x3) {
@@ -41,6 +34,7 @@ __device__ __forceinline__ unsigned pack_fp8x4_vector(float x0, float x1,
     return static_cast<unsigned>(low) | (static_cast<unsigned>(high) << 16);
 }
 
+
 __device__ __forceinline__ void mma_fp8_16832(float d[4],
                                                const unsigned a[4],
                                                const unsigned b[2]) {
@@ -54,23 +48,36 @@ __device__ __forceinline__ void mma_fp8_16832(float d[4],
 #endif
 }
 
-template <bool Transpose>
-__device__ __forceinline__ float load_bf16(
-    const __nv_bfloat16* src, int64_t row, int64_t col,
-    int64_t rows, int64_t cols, float& amax) {
-    if (row >= rows || col >= cols) return 0.0f;
-    int64_t index = Transpose ? col * rows + row : row * cols + col;
-    float value = __bfloat162float(src[index]);
-    amax = fmaxf(amax, fabsf(value));
-    return value;
-}
-
 __device__ __forceinline__ void atomic_max_float(float* destination,
                                                   float value) {
     if (destination)
         atomicMax(reinterpret_cast<unsigned*>(destination), __float_as_uint(value));
 }
 
+__device__ __forceinline__ float warp_reduce_max(float value) {
+#pragma unroll
+    for (int offset = 16; offset; offset >>= 1) {
+        value = fmaxf(value, __shfl_xor_sync(0xffffffffu, value, offset));
+    }
+    return value;
+}
+
+// Block-wide max reduction of a per-warp tracked value, then an atomic
+// update of the global amax slot when `track` is set.
+template <int NWarps>
+__device__ __forceinline__ void block_reduce_amax(float& local, float* slots,
+                                                  int warp, int lane,
+                                                  bool track, float* global) {
+    local = warp_reduce_max(local);
+    if (lane == 0) slots[warp] = local;
+    __syncthreads();
+    if (warp == 0) {
+        float value = lane < NWarps ? slots[lane] : 0.0f;
+        value = warp_reduce_max(value);
+        if (lane == 0 && track && global) atomic_max_float(global, value);
+    }
+}
+
 // One thread moves eight BF16 values (16 bytes). The async copy is issued
 // through a uint4-shaped pointer so the source and destination are both
 // naturally 128-bit aligned for contiguous forward GEMMs.
@@ -83,7 +90,7 @@ __device__ __forceinline__ void cp_async_bf16_8(
                     "r"(valid ? 16 : 0));
 }
 
-template <bool TrackAmax = true, bool VectorPack = true>
+template <bool TrackAmax = true>
 __device__ __forceinline__ unsigned load_fp8x4_from_bf16(
     const __nv_bfloat16* source, float scale_inv, float& amax,
     bool track_amax = true) {
@@ -97,46 +104,13 @@ __device__ __forceinline__ unsigned load_fp8x4_from_bf16(
                              fmaxf(fabsf(x2), fabsf(x3)))));
         }
     }
-    if constexpr (VectorPack) {
+    return pack_fp8x4_vector(x0 * scale_inv, x1 * scale_inv,
-        return pack_fp8x4_vector(x0 * scale_inv, x1 * scale_inv,
+                             x2 * scale_inv, x3 * scale_inv);
-                                 x2 * scale_inv, x3 * scale_inv);
-    } else {
-        return pack_fp8x4_scalar(x0 * scale_inv, x1 * scale_inv,
-                                 x2 * scale_inv, x3 * scale_inv);
-    }
 }
 
-template <bool TransposeA, bool TransposeB>
-__device__ __forceinline__ void load_direct_fragments(
-    const __nv_bfloat16* a, const __nv_bfloat16* b,
-    int64_t row0, int64_t row1, int b_row, int64_t k0,
-    int64_t m, int64_t n, int64_t k, float inv_a, float inv_b,
-    float& amax_a, float& amax_b, unsigned a_frag[4], unsigned b_frag[2]) {
-    auto load_a = [&](int64_t row, int64_t col) {
-        return load_bf16<TransposeA>(a, row, col, m, k, amax_a) * inv_a;
-    };
-    auto load_b = [&](int64_t col) {
-        return load_bf16<TransposeB>(b, b_row, col, n, k, amax_b) * inv_b;
-    };
-    a_frag[0] = pack_fp8x4_scalar(load_a(row0, k0), load_a(row0, k0 + 1),
-                                  load_a(row0, k0 + 2), load_a(row0, k0 + 3));
-    a_frag[1] = pack_fp8x4_scalar(load_a(row1, k0), load_a(row1, k0 + 1),
-                                  load_a(row1, k0 + 2), load_a(row1, k0 + 3));
-    a_frag[2] = pack_fp8x4_scalar(
-        load_a(row0, k0 + 16), load_a(row0, k0 + 17),
-        load_a(row0, k0 + 18), load_a(row0, k0 + 19));
-    a_frag[3] = pack_fp8x4_scalar(
-        load_a(row1, k0 + 16), load_a(row1, k0 + 17),
-        load_a(row1, k0 + 18), load_a(row1, k0 + 19));
-    b_frag[0] = pack_fp8x4_scalar(load_b(k0), load_b(k0 + 1), load_b(k0 + 2),
-                                  load_b(k0 + 3));
-    b_frag[1] = pack_fp8x4_scalar(load_b(k0 + 16), load_b(k0 + 17),
-                                  load_b(k0 + 18), load_b(k0 + 19));
-}
 
-template <bool TransposeA, bool TransposeB, bool AddBias, int BlockM = kBlockM,
+template <bool AddBias, bool TrackAmax>
-          int BlockN = kBlockN, bool TrackAmax = true>
+__global__ void fused_fp8_gemm_fast_kernel(
-__global__ void fused_fp8_gemm_kernel(
     const __nv_bfloat16* __restrict__ a,
     const __nv_bfloat16* __restrict__ b,
     __nv_bfloat16* __restrict__ out,
@@ -146,10 +120,13 @@ __global__ void fused_fp8_gemm_kernel(
     float* __restrict__ amax_a,
     float* __restrict__ amax_b,
     int64_t m, int64_t n, int64_t k) {
-    __shared__ __align__(16) __nv_fp8_e4m3 a_tile[2][BlockM][kMmaK];
+    extern __shared__ char smem[];
-    __shared__ __align__(16) __nv_fp8_e4m3 b_tile[2][BlockN][kMmaK];
+    constexpr int a_stride = kFastBlockM * kFastK;
-    __shared__ __align__(16) __nv_bfloat16 a_bf16[2][BlockM][kMmaK];
+    constexpr int b_stride = kFastBlockN * kFastK;
-    __shared__ __align__(16) __nv_bfloat16 b_bf16[2][BlockN][kMmaK];
+    constexpr int b_bf16_offset = kFastStages * a_stride;
+    auto* a_bf16 = reinterpret_cast<__nv_bfloat16*>(smem);
+    auto* b_bf16 =
+        reinterpret_cast<__nv_bfloat16*>(smem + b_bf16_offset * 2);
     __shared__ float warp_amax_a[kWarps];
     __shared__ float warp_amax_b[kWarps];
 
@@ -158,197 +135,188 @@ __global__ void fused_fp8_gemm_kernel(
     const int lane = tid & 31;
     const int group = lane >> 2;
     const int thread_in_group = lane & 3;
-    constexpr int warps_n = kBlockN / kMmaN;
+    constexpr int warps_n = kFastBlockN / 16;
     const int warp_m = warp / warps_n;
     const int warp_n = warp % warps_n;
-    const int64_t row_base = blockIdx.y * BlockM + warp_m * kMmaM + group;
+    const int64_t row_base =
-    const int64_t output_col = blockIdx.x * BlockN + warp_n * kMmaN +
+        blockIdx.y * kFastBlockM + warp_m * 64 + group;
-                               thread_in_group * 2;
+    const int64_t output_col =
+        blockIdx.x * kFastBlockN + warp_n * 16 + thread_in_group * 2;
     const float sa = *scale_a;
     const float sb = *scale_b;
     const float inv_a = 1.0f / sa;
     const float inv_b = 1.0f / sb;
     float local_amax_a = 0.0f;
     float local_amax_b = 0.0f;
-    float acc[4 * (BlockM / kMmaM) * (BlockN / kBlockN)] = {};
+    float acc[4 * 4 * 2] = {};
 
-    constexpr bool AsyncContiguous = !TransposeA && !TransposeB;
+    const bool track_amax_a = TrackAmax && blockIdx.x == 0;
-    const bool track_amax_a =
+    const bool track_amax_b = TrackAmax && blockIdx.y == 0;
-        TrackAmax && (!AsyncContiguous || blockIdx.x == 0);
+    // Each thread issues 8 A chunks and 4 B chunks of 8 BF16 (16B) per stage.
-    const bool track_amax_b =
+    auto load_tile = [&](int stage, int64_t k_base) {
-        TrackAmax && (!AsyncContiguous || blockIdx.y == 0);
+        const int r0 = tid >> 2;
-    auto load_bf16_tile = [&](int buffer, int64_t k_base) {
+        const int c0 = (tid & 3) * 8;
-        if constexpr (AsyncContiguous) {
+#pragma unroll
-            const bool active_loader = true;
+        for (int j = 0; j < kFastK / 32; ++j) {
-            const int async_row = tid >> 2;
+            const int col = c0 + 32 * j;
-            const int async_col = (tid & 3) * 8;
+            const bool full_chunk = k_base + col + 7 < k;
-            if (active_loader) {
+            const int64_t a_row = blockIdx.y * kFastBlockM + r0;
-                 const int64_t a_row = blockIdx.y * BlockM + async_row;
+            const int64_t b_row = blockIdx.x * kFastBlockN + r0;
-                 const int64_t b_row = blockIdx.x * BlockN + async_row;
+            auto* a_dst = &a_bf16[stage * a_stride + r0 * kFastK + col];
-                const auto* a_source = a + a_row * k + k_base + async_col;
+            auto* b_dst = &b_bf16[stage * b_stride + r0 * kFastK + col];
-                const auto* b_source = b + b_row * k + k_base + async_col;
+            const auto* a_ptr = a + a_row * k + k_base + col;
-                 const bool full_chunk = k_base + async_col + 7 < k;
+            const auto* b_ptr = b + b_row * k + k_base + col;
-                const bool aligned_a =
+            const bool full_a = a_row < m && full_chunk;
-                    (reinterpret_cast<uintptr_t>(a_source) & 15) == 0;
+            const bool full_b = b_row < n && full_chunk;
-                const bool aligned_b =
+            const bool aligned_a =
-                    (reinterpret_cast<uintptr_t>(b_source) & 15) == 0;
+                (reinterpret_cast<uintptr_t>(a_ptr) & 15) == 0;
-                if (a_row < m && full_chunk && aligned_a) {
+            const bool aligned_b =
-                    cp_async_bf16_8(
+                (reinterpret_cast<uintptr_t>(b_ptr) & 15) == 0;
-                        &a_bf16[buffer][async_row][async_col], a_source, true);
+            if (full_a && aligned_a) {
+                cp_async_bf16_8(a_dst, a_ptr, true);
+            } else {
+#pragma unroll
+                for (int i = 0; i < 8; ++i) {
+                    a_dst[i] = a_row < m && k_base + col + i < k
+                                   ? a_ptr[i]
+                                   : __float2bfloat16(0.0f);
+                }
+            }
+            if (full_b && aligned_b) {
+                cp_async_bf16_8(b_dst, b_ptr, true);
+            } else {
+#pragma unroll
+                for (int i = 0; i < 8; ++i) {
+                    b_dst[i] = b_row < n && k_base + col + i < k
+                                   ? b_ptr[i]
+                                   : __float2bfloat16(0.0f);
+                }
+            }
+            if (r0 + 64 < kFastBlockM) {
+                const int64_t a_row_hi = blockIdx.y * kFastBlockM + r0 + 64;
+                auto* a_dst_hi =
+                    &a_bf16[stage * a_stride + (r0 + 64) * kFastK + col];
+                const auto* a_ptr_hi = a + a_row_hi * k + k_base + col;
+                const bool full_a_hi = a_row_hi < m && full_chunk;
+                const bool aligned_a_hi =
+                    (reinterpret_cast<uintptr_t>(a_ptr_hi) & 15) == 0;
+                if (full_a_hi && aligned_a_hi) {
+                    cp_async_bf16_8(a_dst_hi, a_ptr_hi, true);
                 } else {
 #pragma unroll
                     for (int i = 0; i < 8; ++i) {
-                        a_bf16[buffer][async_row][async_col + i] =
+                        a_dst_hi[i] = a_row_hi < m && k_base + col + i < k
-                            a_row < m && k_base + async_col + i < k
+                                          ? a_ptr_hi[i]
-                            ? a_source[i]
+                                          : __float2bfloat16(0.0f);
-                            : __float2bfloat16(0.0f);
-                    }
-                }
-                if (b_row < n && full_chunk && aligned_b) {
-                    cp_async_bf16_8(
-                        &b_bf16[buffer][async_row][async_col], b_source, true);
-                } else if (async_row < BlockN) {
-#pragma unroll
-                    for (int i = 0; i < 8; ++i) {
-                        b_bf16[buffer][async_row][async_col + i] =
-                            b_row < n && k_base + async_col + i < k
-                            ? b_source[i]
-                            : __float2bfloat16(0.0f);
                     }
                 }
             }
         }
     };
 
-    if constexpr (AsyncContiguous) {
+    // Quantize must place each 4-BP8 group at the byte offset the MMA
-        load_bf16_tile(0, 0);
+    // fragment reads: 8*(lane&3) + 64*k_seg for a row. With in-place storage
+    // (fp8 element k lives at byte 2k), the BF16 column of a group is
+    // 4*(tid&7) + 32*j, so partition by 4-element groups instead of the
+    // 8-element cp.async chunks.
+    auto quantize_tile = [&](int stage) {
+        const int r0 = tid >> 3;
+        const int c0 = (tid & 7) * 4;
+#pragma unroll
+        for (int s = 0; s < 4; ++s) {
+            const int row = r0 + 32 * s;
+            auto* a_src = &a_bf16[stage * a_stride + row * kFastK + c0];
+            auto* a_dst = reinterpret_cast<unsigned*>(a_src);
+#pragma unroll
+            for (int j = 0; j < kFastK / 32; ++j) {
+                a_dst[16 * j] = load_fp8x4_from_bf16<TrackAmax>(
+                    a_src + 32 * j, inv_a, local_amax_a, track_amax_a);
+            }
+        }
+#pragma unroll
+        for (int s = 0; s < 2; ++s) {
+            const int row = r0 + 32 * s;
+            auto* b_src = &b_bf16[stage * b_stride + row * kFastK + c0];
+            auto* b_dst = reinterpret_cast<unsigned*>(b_src);
+#pragma unroll
+            for (int j = 0; j < kFastK / 32; ++j) {
+                b_dst[16 * j] = load_fp8x4_from_bf16<TrackAmax>(
+                    b_src + 32 * j, inv_b, local_amax_b, track_amax_b);
+            }
+        }
+    };
+
+    const int64_t tile_count = (k + kFastK - 1) / kFastK;
+    load_tile(0, 0);
+    asm volatile("cp.async.commit_group;");
+    if (tile_count > 1) {
+        load_tile(1, kFastK);
         asm volatile("cp.async.commit_group;");
-        asm volatile("cp.async.wait_group 0;");
-        __syncthreads();
     }
-
-    const int64_t tile_count = (k + kMmaK - 1) / kMmaK;
     for (int64_t tile_index = 0; tile_index < tile_count; ++tile_index) {
-        const int buffer = tile_index & 1;
+        const int stage = static_cast<int>(tile_index % kFastStages);
-        const int64_t k_base = tile_index * kMmaK;
+        if (tile_index + 1 == tile_count) {
-        if constexpr (AsyncContiguous) {
+            asm volatile("cp.async.wait_group 0;");
-            if (tile_index + 1 < tile_count) {
-                load_bf16_tile(buffer ^ 1, k_base + kMmaK);
-                asm volatile("cp.async.commit_group;");
-            }
-            // Quantization is performed from the prefetched BF16 tile while
-            // the next tile is in flight. No FP8 global temporary is used.
-            const int quant_row = tid >> 2;
-            const int quant_col = (tid & 3) * 8;
-            const __nv_bfloat16* a_source =
-                &a_bf16[buffer][quant_row][quant_col];
-            *reinterpret_cast<unsigned*>(&a_tile[buffer][quant_row][quant_col]) =
-                load_fp8x4_from_bf16<TrackAmax, !TransposeA && !TransposeB>(
-                    a_source, inv_a, local_amax_a, track_amax_a);
-            *reinterpret_cast<unsigned*>(&a_tile[buffer][quant_row][quant_col + 4]) =
-                load_fp8x4_from_bf16<TrackAmax, !TransposeA && !TransposeB>(
-                    a_source + 4, inv_a, local_amax_a, track_amax_a);
-            if (quant_row < BlockN) {
-                const __nv_bfloat16* b_source =
-                    &b_bf16[buffer][quant_row][quant_col];
-                *reinterpret_cast<unsigned*>(
-                    &b_tile[buffer][quant_row][quant_col]) =
-                    load_fp8x4_from_bf16<TrackAmax, !TransposeA && !TransposeB>(
-                        b_source, inv_b, local_amax_b, track_amax_b);
-                *reinterpret_cast<unsigned*>(
-                    &b_tile[buffer][quant_row][quant_col + 4]) =
-                    load_fp8x4_from_bf16<TrackAmax, !TransposeA && !TransposeB>(
-                        b_source + 4, inv_b, local_amax_b, track_amax_b);
-            }
         } else {
-            const int64_t k0 = k_base + thread_in_group * 4;
+            asm volatile("cp.async.wait_group 1;");
-            const int b_row = blockIdx.x * BlockN + warp_n * kMmaN + group;
-            unsigned a_direct[4];
-            unsigned b_direct[2];
-            load_direct_fragments<TransposeA, TransposeB>(
-                a, b, row_base, row_base + 8, b_row, k0, m, n, k, inv_a, inv_b,
-                local_amax_a, local_amax_b, a_direct, b_direct);
-            mma_fp8_16832(acc, a_direct, b_direct);
-            continue;
         }
+        // wait_group only waits for this thread's async copies. All threads
+        // must finish loading before the tile is read by the CTA.
+        __syncthreads();
+        quantize_tile(stage);
         __syncthreads();
 
-        const int fragment_col = thread_in_group * 4;
+        // Four m16n8k32 MMA segments per 128-K stage.
-        const int a_row0 = warp_m * kMmaM + group;
-        const int a_row1 = a_row0 + 8;
 #pragma unroll
-        for (int n_tile = 0; n_tile < BlockN / kBlockN; ++n_tile) {
+        for (int k_seg = 0; k_seg < kFastK / kMmaK; ++k_seg) {
-            const int b_row = warp_n * kMmaN + group + n_tile * kBlockN;
+            const int frag_col = thread_in_group * 4 + k_seg * 32;
-            unsigned b_frag[2];
-            b_frag[0] = *reinterpret_cast<unsigned*>(
-                &b_tile[buffer][b_row][fragment_col]);
-            b_frag[1] = *reinterpret_cast<unsigned*>(
-                &b_tile[buffer][b_row][fragment_col + 16]);
 #pragma unroll
-            for (int m_tile = 0; m_tile < BlockM / kBlockM; ++m_tile) {
+            for (int nt = 0; nt < 2; ++nt) {
-                const int m_offset = m_tile * kBlockM;
+                const int b_row = warp_n * 16 + nt * 8 + group;
-                unsigned a_frag[4];
+                unsigned b_frag[2];
-                a_frag[0] = *reinterpret_cast<unsigned*>(
+                b_frag[0] = *reinterpret_cast<const unsigned*>(
-                    &a_tile[buffer][a_row0 + m_offset][fragment_col]);
+                    &b_bf16[stage * b_stride + b_row * kFastK + frag_col]);
-                a_frag[1] = *reinterpret_cast<unsigned*>(
+                b_frag[1] = *reinterpret_cast<const unsigned*>(
-                    &a_tile[buffer][a_row1 + m_offset][fragment_col]);
+                    &b_bf16[stage * b_stride + b_row * kFastK + frag_col + 16]);
-                a_frag[2] = *reinterpret_cast<unsigned*>(
+#pragma unroll
-                    &a_tile[buffer][a_row0 + m_offset][fragment_col + 16]);
+                for (int mt = 0; mt < 4; ++mt) {
-                a_frag[3] = *reinterpret_cast<unsigned*>(
+                    const int a_row0 = warp_m * 64 + mt * 16 + group;
-                    &a_tile[buffer][a_row1 + m_offset][fragment_col + 16]);
+                    unsigned a_frag[4];
-                mma_fp8_16832(
+                    a_frag[0] = *reinterpret_cast<const unsigned*>(
-                    acc + (n_tile * (BlockM / kBlockM) + m_tile) * 4,
+                        &a_bf16[stage * a_stride + a_row0 * kFastK + frag_col]);
-                    a_frag, b_frag);
+                    a_frag[1] = *reinterpret_cast<const unsigned*>(
-            }
+                        &a_bf16[stage * a_stride + (a_row0 + 8) * kFastK + frag_col]);
-        }
+                    a_frag[2] = *reinterpret_cast<const unsigned*>(
-        if constexpr (AsyncContiguous) {
+                        &a_bf16[stage * a_stride + a_row0 * kFastK + frag_col + 16]);
-            if (tile_index + 1 < tile_count) {
+                    a_frag[3] = *reinterpret_cast<const unsigned*>(
-                asm volatile("cp.async.wait_group 0;");
+                        &a_bf16[stage * a_stride + (a_row0 + 8) * kFastK + frag_col + 16]);
+                    mma_fp8_16832(acc + (nt * 4 + mt) * 4, a_frag, b_frag);
+                }
             }
         }
         __syncthreads();
+        if (tile_index + 2 < tile_count) {
+            load_tile(stage, (tile_index + 2) * kFastK);
+            asm volatile("cp.async.commit_group;");
+        }
     }
 
     if constexpr (TrackAmax) {
-    for (int offset = 16; offset; offset >>= 1) {
+    block_reduce_amax<kWarps>(local_amax_a, warp_amax_a, warp, lane,
-        local_amax_a = fmaxf(local_amax_a,
+                              track_amax_a, amax_a);
-                             __shfl_xor_sync(0xffffffffu, local_amax_a, offset));
+    block_reduce_amax<kWarps>(local_amax_b, warp_amax_b, warp, lane,
-        local_amax_b = fmaxf(local_amax_b,
+                              track_amax_b, amax_b);
-                             __shfl_xor_sync(0xffffffffu, local_amax_b, offset));
-    }
-    if (lane == 0) {
-        warp_amax_a[warp] = local_amax_a;
-        warp_amax_b[warp] = local_amax_b;
-    }
-    __syncthreads();
-    if (warp == 0) {
-        float block_amax_a = lane < kWarps ? warp_amax_a[lane] : 0.0f;
-        float block_amax_b = lane < kWarps ? warp_amax_b[lane] : 0.0f;
-        for (int offset = 16; offset; offset >>= 1) {
-            block_amax_a = fmaxf(
-                block_amax_a,
-                __shfl_xor_sync(0xffffffffu, block_amax_a, offset));
-            block_amax_b = fmaxf(
-                block_amax_b,
-                __shfl_xor_sync(0xffffffffu, block_amax_b, offset));
-        }
-        if (lane == 0) {
-            if (track_amax_a) atomic_max_float(amax_a, block_amax_a);
-            if (track_amax_b) atomic_max_float(amax_b, block_amax_b);
-        }
-    }
     }
 
     const float output_scale = sa * sb;
 #pragma unroll
-    for (int n_tile = 0; n_tile < BlockN / kBlockN; ++n_tile) {
+    for (int nt = 0; nt < 2; ++nt) {
-        const int64_t col = output_col + n_tile * kBlockN;
+        const int64_t col = output_col + nt * 8;
 #pragma unroll
-        for (int m_tile = 0; m_tile < BlockM / kBlockM; ++m_tile) {
+        for (int mt = 0; mt < 4; ++mt) {
-            const int64_t row0 = row_base + m_tile * kBlockM;
+            const int64_t row0 = row_base + mt * 16;
             const int64_t row1 = row0 + 8;
-            float* tile_acc =
+            float* tile_acc = acc + (nt * 4 + mt) * 4;
-                acc + (n_tile * (BlockM / kBlockM) + m_tile) * 4;
             if (col < n) {
                 float bias0 = 0.0f;
                 float bias1 = 0.0f;
@@ -376,22 +344,210 @@ __global__ void fused_fp8_gemm_kernel(
     }
 }
 
-template <bool TransposeA, bool TransposeB, bool AddBias = false,
+// Pre-quantized FP8-in path: FP8 A/B read straight into shared memory (no
-          int BlockM = kBlockM, int BlockN = kBlockN, bool TrackAmax = true>
+// BF16 staging, no inline quantization), FP32 accumulation, BF16 output.
-void launch_fused_fp8_gemm(
+// Same 128x64 CTA / 64x16 warp tile geometry as the fused kernel; the fp8
+// tile is compact (row = kFastK bytes) so MMA fragments read directly.
+constexpr int kPqBlockM = 128;
+constexpr int kPqBlockN = 64;
+constexpr int kPqK = 32;
+constexpr int kPqStages = 3;
+
+template <typename T>
+__device__ __forceinline__ void cp_async_16b(T* destination,
+                                             const T* source, bool valid) {
+    const unsigned shared_address = __cvta_generic_to_shared(destination);
+    const uint4* source_vec = reinterpret_cast<const uint4*>(source);
+    asm volatile("cp.async.cg.shared.global [%0], [%1], 16, %2;"
+                 :: "r"(shared_address), "l"(source_vec),
+                    "r"(valid ? 16 : 0));
+}
+
+template <bool OutFp8>
+__global__ void fp8_mm_pq_kernel(
+    const __nv_fp8_e4m3* __restrict__ a,
+    const __nv_fp8_e4m3* __restrict__ b,
+    __nv_bfloat16* __restrict__ out_bf16,
+    __nv_fp8_e4m3* __restrict__ out_fp8,
+    const float scale, const float out_scale,
+    int64_t m, int64_t n, int64_t k) {
+    __shared__ __align__(16) __nv_fp8_e4m3 a_tile[kPqStages][kPqBlockM][kPqK];
+    __shared__ __align__(16) __nv_fp8_e4m3 b_tile[kPqStages][kPqBlockN][kPqK];
+
+    const int tid = threadIdx.x;
+    const int warp = tid >> 5;
+    const int lane = tid & 31;
+    const int group = lane >> 2;
+    const int thread_in_group = lane & 3;
+    constexpr int warps_n = kPqBlockN / 16;
+    const int warp_m = warp / warps_n;
+    const int warp_n = warp % warps_n;
+    const int64_t row_base = blockIdx.y * kPqBlockM + warp_m * 64 + group;
+    const int64_t output_col =
+        blockIdx.x * kPqBlockN + warp_n * 16 + thread_in_group * 2;
+    float acc[4 * 4 * 2] = {};
+
+    // One A chunk (16 FP8) per thread covers the 128x32 tile; the first 128
+    // threads issue the 64x32 B chunks.
+    auto load_tile = [&](int stage, int64_t k_base) {
+        const int r0 = tid >> 1;
+        const int c0 = (tid & 1) * 16;
+        const bool full_chunk = k_base + c0 + 15 < k;
+        const int64_t a_row = blockIdx.y * kPqBlockM + r0;
+        auto* a_dst = &a_tile[stage][r0][c0];
+        const auto* a_ptr = a + a_row * k + k_base + c0;
+        const bool full_a = a_row < m && full_chunk;
+        const bool aligned_a =
+            (reinterpret_cast<uintptr_t>(a_ptr) & 15) == 0;
+        if (full_a && aligned_a) {
+            cp_async_16b(a_dst, a_ptr, true);
+        } else {
+#pragma unroll
+            for (int i = 0; i < 16; ++i) {
+                a_dst[i] = a_row < m && k_base + c0 + i < k
+                               ? a_ptr[i]
+                               : __nv_fp8_e4m3(0.0f);
+            }
+        }
+        if (tid < 128) {
+            const int64_t b_row = blockIdx.x * kPqBlockN + r0;
+            auto* b_dst = &b_tile[stage][r0][c0];
+            const auto* b_ptr = b + b_row * k + k_base + c0;
+            const bool full_b = b_row < n && full_chunk;
+            const bool aligned_b =
+                (reinterpret_cast<uintptr_t>(b_ptr) & 15) == 0;
+            if (full_b && aligned_b) {
+                cp_async_16b(b_dst, b_ptr, true);
+            } else {
+#pragma unroll
+                for (int i = 0; i < 16; ++i) {
+                    b_dst[i] = b_row < n && k_base + c0 + i < k
+                                   ? b_ptr[i]
+                                   : __nv_fp8_e4m3(0.0f);
+                }
+            }
+        }
+    };
+
+    const int64_t tile_count = (k + kPqK - 1) / kPqK;
+    load_tile(0, 0);
+    asm volatile("cp.async.commit_group;");
+    if (tile_count > 1) {
+        load_tile(1, kPqK);
+        asm volatile("cp.async.commit_group;");
+    }
+    if (tile_count > 2) {
+        load_tile(2, 2 * kPqK);
+        asm volatile("cp.async.commit_group;");
+    }
+    for (int64_t tile_index = 0; tile_index < tile_count; ++tile_index) {
+        const int stage = static_cast<int>(tile_index % kPqStages);
+        const int64_t remaining = tile_count - tile_index - 1;
+        if (remaining >= 2) {
+            asm volatile("cp.async.wait_group 2;");
+        } else if (remaining == 1) {
+            asm volatile("cp.async.wait_group 1;");
+        } else {
+            asm volatile("cp.async.wait_group 0;");
+        }
+        // Barrier 1: every thread's cp.async for this stage is complete
+        // before any thread reads tiles written by other threads.
+        __syncthreads();
+
+#pragma unroll
+        for (int k_seg = 0; k_seg < kPqK / kMmaK; ++k_seg) {
+            const int frag_col = thread_in_group * 4 + k_seg * 32;
+#pragma unroll
+            for (int nt = 0; nt < 2; ++nt) {
+                const int b_row = warp_n * 16 + nt * 8 + group;
+                unsigned b_frag[2];
+                b_frag[0] = *reinterpret_cast<const unsigned*>(
+                    &b_tile[stage][b_row][frag_col]);
+                b_frag[1] = *reinterpret_cast<const unsigned*>(
+                    &b_tile[stage][b_row][frag_col + 16]);
+#pragma unroll
+                for (int mt = 0; mt < 4; ++mt) {
+                    const int a_row0 = warp_m * 64 + mt * 16 + group;
+                    unsigned a_frag[4];
+                    a_frag[0] = *reinterpret_cast<const unsigned*>(
+                        &a_tile[stage][a_row0][frag_col]);
+                    a_frag[1] = *reinterpret_cast<const unsigned*>(
+                        &a_tile[stage][a_row0 + 8][frag_col]);
+                    a_frag[2] = *reinterpret_cast<const unsigned*>(
+                        &a_tile[stage][a_row0][frag_col + 16]);
+                    a_frag[3] = *reinterpret_cast<const unsigned*>(
+                        &a_tile[stage][a_row0 + 8][frag_col + 16]);
+                    mma_fp8_16832(acc + (nt * 4 + mt) * 4, a_frag, b_frag);
+                }
+            }
+        }
+        // Barrier 2: every thread finished reading this stage's tiles before
+        // the prefetch for the (i+3)-th tile overwrites them.
+        __syncthreads();
+        if (tile_index + 3 < tile_count) {
+            load_tile(stage, (tile_index + 3) * kPqK);
+            asm volatile("cp.async.commit_group;");
+        }
+    }
+
+    const float output_scale = scale * out_scale;
+#pragma unroll
+    for (int nt = 0; nt < 2; ++nt) {
+        const int64_t col = output_col + nt * 8;
+        // Per-row store: FP8 packs two adjacent columns into one 16-bit
+        // write; the BF16 path writes two scalars. Boundary columns fall
+        // back to a scalar convert so the pack never crosses the row edge.
+        auto store_out = [&](int64_t row, float v0, float v1) {
+            if (row >= m) return;
+            if constexpr (OutFp8) {
+                if (col + 1 < n) {
+                    *reinterpret_cast<unsigned short*>(
+                        out_fp8 + row * n + col) =
+                        static_cast<unsigned short>(__nv_cvt_float2_to_fp8x2(
+                            make_float2(v0 * output_scale, v1 * output_scale),
+                            __NV_SATFINITE, __NV_E4M3));
+                } else {
+                    out_fp8[row * n + col] = __nv_fp8_e4m3(v0 * output_scale);
+                }
+            } else {
+                out_bf16[row * n + col] = __float2bfloat16(v0 * scale);
+                if (col + 1 < n)
+                    out_bf16[row * n + col + 1] = __float2bfloat16(v1 * scale);
+            }
+        };
+#pragma unroll
+        for (int mt = 0; mt < 4; ++mt) {
+            const int64_t row0 = row_base + mt * 16;
+            float* tile_acc = acc + (nt * 4 + mt) * 4;
+            if (col < n) {
+                store_out(row0, tile_acc[0], tile_acc[1]);
+                store_out(row0 + 8, tile_acc[2], tile_acc[3]);
+            }
+        }
+    }
+}
+
+template <bool AddBias = false, bool TrackAmax = true>
+void launch_fused_fp8_gemm_fast(
     const torch::Tensor& a, const torch::Tensor& b, torch::Tensor& out,
     const torch::Tensor& bias, const torch::Tensor& scale_a,
     const torch::Tensor& scale_b, torch::Tensor* amax_a,
     torch::Tensor* amax_b, int64_t m, int64_t n, int64_t k,
     cudaStream_t stream) {
-    dim3 grid((n + BlockN - 1) / BlockN,
+    dim3 grid((n + kFastBlockN - 1) / kFastBlockN,
-              (m + BlockM - 1) / BlockM);
+              (m + kFastBlockM - 1) / kFastBlockM);
     const auto* bias_ptr = AddBias
         ? reinterpret_cast<const __nv_bfloat16*>(bias.data_ptr())
         : nullptr;
-    fused_fp8_gemm_kernel<TransposeA, TransposeB, AddBias, BlockM, BlockN,
+    auto kernel = fused_fp8_gemm_fast_kernel<AddBias, TrackAmax>;
-                          TrackAmax>
+    static bool attribute_set = false;
-        <<<grid, kWarps * 32, 0, stream>>>(
+    if (!attribute_set) {
+        C10_CUDA_CHECK(cudaFuncSetAttribute(
+            kernel, cudaFuncAttributeMaxDynamicSharedMemorySize,
+            kFastSmemBytes));
+        attribute_set = true;
+    }
+    kernel<<<grid, kWarps * 32, kFastSmemBytes, stream>>>(
         reinterpret_cast<const __nv_bfloat16*>(a.data_ptr()),
         reinterpret_cast<const __nv_bfloat16*>(b.data_ptr()),
         reinterpret_cast<__nv_bfloat16*>(out.data_ptr()), bias_ptr,
@@ -453,8 +609,7 @@ torch::Tensor fp8_mm(torch::Tensor a, torch::Tensor b, torch::Tensor sx,
     auto b_c = b.contiguous();
     auto out = torch::empty({a_c.size(0), b_c.size(0)}, a_c.options());
     torch::Tensor no_bias;
-    launch_fused_fp8_gemm<false, false, false, kForwardBlockM,
+    launch_fused_fp8_gemm_fast<false, false>(
-                          kForwardBlockN, false>(
         a_c, b_c, out, no_bias, sx, sw, nullptr, nullptr,
         a_c.size(0), b_c.size(0), a_c.size(1), stream.stream());
     C10_CUDA_CHECK(cudaGetLastError());
@@ -490,13 +645,11 @@ torch::Tensor fp8_linear_forward_scaled(
                         bias.scalar_type() == torch::kBFloat16 &&
                         bias.numel() == n,
                     "bias must be CUDA bf16 with shape [N]");
-        launch_fused_fp8_gemm<false, false, true, kForwardBlockM,
+        launch_fused_fp8_gemm_fast<true, true>(
-                              kForwardBlockN>(
             x_c, w_c, out, bias, sx, sw, &amax_x, &amax_w,
             m, n, k, stream.stream());
     } else {
-        launch_fused_fp8_gemm<false, false, false, kForwardBlockM,
+        launch_fused_fp8_gemm_fast<false, true>(
-                              kForwardBlockN>(
             x_c, w_c, out, bias, sx, sw, &amax_x, &amax_w,
             m, n, k, stream.stream());
     }
@@ -542,16 +695,27 @@ std::tuple<torch::Tensor, torch::Tensor, torch::Tensor> fp8_linear_backward_scal
     bool recorded_amax = false;
     if (masks[0]) {
         auto grad_input_2d = grad_input.reshape({m, k});
-        launch_fused_fp8_gemm<false, true>(
+        // The fast kernel computes A @ B^T. A contiguous W^T makes dX use
-            g_c, w_c, grad_input_2d, no_bias, sg, sw, &amax_g, nullptr,
+        // the same coalesced forward tile path instead of scalar fragments.
+        auto w_t = w_c.transpose(0, 1).contiguous();
+        launch_fused_fp8_gemm_fast<false, true>(
+            g_c, w_t, grad_input_2d, no_bias, sg, sw, &amax_g, nullptr,
             m, k, n, stream.stream());
         recorded_amax = true;
     }
     if (masks[1]) {
-        launch_fused_fp8_gemm<true, true>(
+        // dW = G^T @ X, expressed as (G^T) @ (X^T)^T for the same kernel.
-            g_c, x_c, grad_weight, no_bias, sg, sx,
+        auto g_t = g_c.transpose(0, 1).contiguous();
-            recorded_amax ? nullptr : &amax_g, nullptr,
+        auto x_t = x_c.transpose(0, 1).contiguous();
-            n, k, m, stream.stream());
+        if (recorded_amax) {
+            launch_fused_fp8_gemm_fast<false, false>(
+                g_t, x_t, grad_weight, no_bias, sg, sx, nullptr, nullptr,
+                n, k, m, stream.stream());
+        } else {
+            launch_fused_fp8_gemm_fast<false, true>(
+                g_t, x_t, grad_weight, no_bias, sg, sx, &amax_g, nullptr,
+                n, k, m, stream.stream());
+        }
         recorded_amax = true;
     }
     if (!recorded_amax) {
@@ -566,10 +730,80 @@ std::tuple<torch::Tensor, torch::Tensor, torch::Tensor> fp8_linear_backward_scal
     return {grad_input, grad_weight, grad_bias};
 }
 
+torch::Tensor fp8_mm_prequant(torch::Tensor a, torch::Tensor b,
+                              torch::Tensor scale) {
+    TORCH_CHECK(a.is_cuda() && b.is_cuda(), "CUDA tensors required");
+    TORCH_CHECK(a.scalar_type() == torch::kFloat8_e4m3fn &&
+                    b.scalar_type() == torch::kFloat8_e4m3fn,
+                "a and b must be fp8_e4m3fn");
+    TORCH_CHECK(a.dim() == 2 && b.dim() == 2, "a and b must be 2D");
+    TORCH_CHECK(a.device() == b.device(), "a and b must be on the same device");
+    TORCH_CHECK(a.size(1) == b.size(1), "inner dim mismatch");
+    check_scale(scale, a, "scale");
+    check_fp8_device(a);
+    const at::cuda::OptionalCUDAGuard guard(a.device());
+    auto stream = at::cuda::getCurrentCUDAStream();
+
+    auto a_c = a.contiguous();
+    auto b_c = b.contiguous();
+    int64_t m = a_c.size(0), k = a_c.size(1), n = b_c.size(0);
+    auto out = torch::empty({m, n},
+                            a_c.options().dtype(torch::kBFloat16));
+    const float scale_value = scale.item<float>();
+    dim3 grid((n + kPqBlockN - 1) / kPqBlockN,
+              (m + kPqBlockM - 1) / kPqBlockM);
+    fp8_mm_pq_kernel<false><<<grid, kWarps * 32, 0, stream>>>(
+        reinterpret_cast<const __nv_fp8_e4m3*>(a_c.data_ptr()),
+        reinterpret_cast<const __nv_fp8_e4m3*>(b_c.data_ptr()),
+        reinterpret_cast<__nv_bfloat16*>(out.data_ptr()), nullptr,
+        scale_value, 1.0f, m, n, k);
+    C10_CUDA_CHECK(cudaGetLastError());
+    return out;
+}
+
+torch::Tensor fp8_mm_prequant_fp8(torch::Tensor a, torch::Tensor b,
+                                  torch::Tensor scale,
+                                  torch::Tensor out_scale) {
+    TORCH_CHECK(a.is_cuda() && b.is_cuda(), "CUDA tensors required");
+    TORCH_CHECK(a.scalar_type() == torch::kFloat8_e4m3fn &&
+                    b.scalar_type() == torch::kFloat8_e4m3fn,
+                "a and b must be fp8_e4m3fn");
+    TORCH_CHECK(a.dim() == 2 && b.dim() == 2, "a and b must be 2D");
+    TORCH_CHECK(a.device() == b.device(), "a and b must be on the same device");
+    TORCH_CHECK(a.size(1) == b.size(1), "inner dim mismatch");
+    check_scale(scale, a, "scale");
+    check_scale(out_scale, a, "out_scale");
+    check_fp8_device(a);
+    const at::cuda::OptionalCUDAGuard guard(a.device());
+    auto stream = at::cuda::getCurrentCUDAStream();
+
+    auto a_c = a.contiguous();
+    auto b_c = b.contiguous();
+    int64_t m = a_c.size(0), k = a_c.size(1), n = b_c.size(0);
+    auto out = torch::empty({m, n}, a_c.options());
+    const float scale_value = scale.item<float>();
+    const float out_scale_value = out_scale.item<float>();
+    dim3 grid((n + kPqBlockN - 1) / kPqBlockN,
+              (m + kPqBlockM - 1) / kPqBlockM);
+    fp8_mm_pq_kernel<true><<<grid, kWarps * 32, 0, stream>>>(
+        reinterpret_cast<const __nv_fp8_e4m3*>(a_c.data_ptr()),
+        reinterpret_cast<const __nv_fp8_e4m3*>(b_c.data_ptr()), nullptr,
+        reinterpret_cast<__nv_fp8_e4m3*>(out.data_ptr()),
+        scale_value, out_scale_value, m, n, k);
+    C10_CUDA_CHECK(cudaGetLastError());
+    return out;
+}
+
 PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
     m.def("fp8_mm", &fp8_mm, py::arg("a"), py::arg("b"), py::arg("sx"),
           py::arg("sw"),
           "Fused BF16 input, E4M3 MMA, FP32 accumulation, BF16 output GEMM");
+    m.def("fp8_mm_prequant", &fp8_mm_prequant, py::arg("a"), py::arg("b"),
+          py::arg("scale"),
+          "Pre-quantized FP8 GEMM with FP32 accumulation and BF16 output");
+    m.def("fp8_mm_prequant_fp8", &fp8_mm_prequant_fp8, py::arg("a"),
+          py::arg("b"), py::arg("scale"), py::arg("out_scale"),
+          "Pre-quantized FP8 GEMM with FP32 accumulation and FP8 output");
     m.def("fp8_linear_forward_scaled", &fp8_linear_forward_scaled,
           py::arg("x"), py::arg("w"), py::arg("bias"), py::arg("sx"),
           py::arg("sw"), py::arg("sx_inv"), py::arg("sw_inv"),

tests/extension/test_fp8_mma.py

@@ -94,3 +94,63 @@ def test_fused_fp8_linear_forward_and_backward():
     torch.testing.assert_close(amax_x, x.abs().amax().float().reshape(1))
     torch.testing.assert_close(amax_w, weight.abs().amax().float().reshape(1))
     torch.testing.assert_close(amax_g, grad.abs().amax().float().reshape(1))
+
+
+def test_fp8_mm_prequant_matches_scaled_mm():
+    torch.manual_seed(11)
+    m, n, k = 512, 4096, 4096
+    a = torch.randn(m, k, device="cuda", dtype=torch.bfloat16)
+    weight = torch.randn(n, k, device="cuda", dtype=torch.bfloat16)
+    a8 = a.to(torch.float8_e4m3fn)
+    w8 = weight.to(torch.float8_e4m3fn)
+    scale = torch.tensor([2.5], device="cuda")
+
+    out = get_module("fp8_mm").fp8_mm_prequant(a8, w8, scale)
+
+    # Reference via fp64: FP8 quantization error is dominated by the 3-bit
+    # mantissa, so the tolerance must track the input quantization scale.
+    ref = (a8.float().double() @ w8.float().double().t() * 2.5).to(torch.bfloat16)
+    assert out.dtype == torch.bfloat16
+    assert out.shape == (m, n)
+    torch.testing.assert_close(out, ref, atol=6.0, rtol=0.05)
+
+    # Cross-check against torch's native FP8 GEMM on identical inputs.
+    try:
+        torch._scaled_mm(
+            a8,
+            w8.t(),
+            torch.full((m, 1), 2.5, device="cuda"),
+            torch.ones((1, n), device="cuda"),
+            out_dtype=torch.bfloat16,
+        )
+    except (RuntimeError, NotImplementedError):
+        return
+    torch.testing.assert_close(
+        out,
+        torch._scaled_mm(
+            a8,
+            w8.t(),
+            torch.full((m, 1), 2.5, device="cuda"),
+            torch.ones((1, n), device="cuda"),
+            out_dtype=torch.bfloat16,
+        ),
+        atol=2.0,
+        rtol=0.01,
+    )
+
+
+def test_fp8_mm_prequant_fp8_output():
+    torch.manual_seed(13)
+    m, n, k = 512, 4096, 4096
+    a = torch.randn(m, k, device="cuda", dtype=torch.bfloat16)
+    weight = torch.randn(n, k, device="cuda", dtype=torch.bfloat16)
+    a8 = a.to(torch.float8_e4m3fn)
+    w8 = weight.to(torch.float8_e4m3fn)
+    scale = torch.tensor([2.5], device="cuda")
+    out_scale = torch.tensor([0.1], device="cuda")
+
+    out = get_module("fp8_mm").fp8_mm_prequant_fp8(a8, w8, scale, out_scale)
+    assert out.dtype == torch.float8_e4m3fn
+    assert out.shape == (m, n)
+    ref = (a8.float().double() @ w8.float().double().t() * 2.5 * 0.1).to(torch.bfloat16)
+    torch.testing.assert_close(out.float().to(torch.bfloat16), ref, atol=1.0, rtol=0.05)