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perf: speed up fp8 gemm tiles and scheduling

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- K tile 32->64 (new default): fewer barriers, more MMA per stage; generalize tile_at swizzle and load_operand_tile accordingly
- 64x128 small-M CTA for m<=64 (2x at 64x4096x4096)
- L2 rasterization for crosswise-A layouts (+6..21%)
- micro-bench: NT 4096^3 +35%; linear fwd 1.24-1.76x, bwd 1.71-2.27x vs bf16
- add csrc/tests/fp8_test.cu (single MMA demo + GEMM layouts x K-tiles vs CPU reference)
This commit is contained in:
ViperEkura
2026-08-24 18:29:55 +08:00
parent d5067af064
commit 74e694921c
3 changed files with 491 additions and 244 deletions
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csrc/kernels/fp8/gemm.cuh
+179 -98
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@@ -21,6 +21,14 @@ namespace fp8 {
constexpr int kMmaK = 32;
constexpr int kWarps = 8; // 128x128 CTA = 8 warps
// log2 of a compile-time power of two (for tile_at's swizzle shift).
template <int N, int Acc = 0>
struct log2_const : log2_const<(N >> 1), Acc + 1> {};
template <int Acc>
struct log2_const<1, Acc> {
static constexpr int value = Acc;
};
// Map the FP8Format enum to the CUDA fp8 element type consumed by mma_sync.
template <FP8Format Fmt>
struct fp8_input {
@@ -118,22 +126,26 @@ __global__ void fp8_quantize_kernel(FP8Params p) {
}
// Swizzled address inside a flat [rows * K] staging tile: the 16-byte chunk
// index is XORed with row bits starting at bit 2. Unswizzled, a kK=32 row
// spans only 8 words, so a warp's fragment load (8 consecutive rows x 4B,
// e.g. a_row0+0..7) maps rows r and r+4 onto the same banks — a 2-way
// conflict on every LDS. XORing the chunk index with row bit 2 shifts rows
// 4..7 by one chunk so each warp's 32-word read hits all 32 banks exactly
// once. Chunks stay contiguous, so the cp.async 16B staging path is
// unaffected. Validated for kK=32 (2 chunks); larger power-of-two chunk
// counts compile but need their own bank analysis.
// index is XORed with a row-dependent slice so a warp's fragment load (8
// consecutive rows x 16B) hits all 32 banks exactly once. With kChunks
// power-of-two chunks per row, the XOR source is the top log2(kChunks) bits
// of the row index within each group of 8:
// kChunks=2 -> row bits [3] (K=32: rows r and r+4 diverge)
// kChunks=4 -> row bits [2:1] (K=64: rows diverge every 2)
// kChunks=8 -> row bits [2:0] (K=128: every row)
// (row word-stride is K/4 words = 4*kChunks, so unswizzled rows r and
// r + 8/kChunks collide mod 32 banks; the XOR spreads the 8 rows of one
// ldmatrix matrix across the 8 distinct 4-bank groups.) Chunks stay
// contiguous, so the cp.async 16B staging path is unaffected.
template <int K, typename T8>
__device__ __forceinline__ T8* tile_at(T8* tile, int row, int col) {
constexpr int kChunks = K / 16; // 16B chunks per row
static_assert(kChunks >= 1 && (kChunks & (kChunks - 1)) == 0,
"swizzle needs a power-of-two 16B-chunk count");
constexpr int kShift = 3 - log2_const<kChunks>::value;
return tile + row * K
+ ((((col >> 4) ^ ((row >> 2) & (kChunks - 1))) << 4)
+ (col & 15));
+ ((((col >> 4) ^ ((row >> kShift) & (kChunks - 1))) << 4)
+ (col & 15));
}
// Stage-load one GEMM operand into the canonical flat [rows * K] shared tile
@@ -142,74 +154,88 @@ __device__ __forceinline__ T8* tile_at(T8* tile, int row, int col) {
// layout: RowMajor (stored [rows][contract]) copies 16-byte K-contiguous runs
// with cp.async, while ColMajor (stored [contract][rows]) reads 16-byte runs
// along the operand's contiguous non-contract dim and scatters them across
// the tile's rows. `block_row` is this block's origin in the operand's row
// dim; the caller restricts which threads invoke it (all threads for A, the
// first 128 for B).
template <typename T8, int K, typename Layout>
// the tile's rows. RowsTile is the tile's row capacity (kBlockM / kBlockN)
// and kThreads the CTA size; the runtime `rows` bound may be smaller (tail
// predication). `block_row` is this block's origin in the operand's row dim.
template <typename T8, int K, typename Layout, int RowsTile, int kThreads>
__device__ __forceinline__ void load_operand_tile(
T8* tile, const T8* __restrict__ operand, int64_t rows,
int64_t contract, int64_t ld, int tid, int64_t k_base,
int64_t block_row) {
constexpr int kChunks = K / 16;
static_assert(RowsTile * kChunks % kThreads == 0,
"tile chunks must divide evenly across threads");
constexpr int kCpt = RowsTile * kChunks / kThreads; // chunks per thread
if constexpr (std::is_same_v<Layout, ColMajor>) {
// Operand stored [contract][rows]: contiguous along the non-contract dim.
const int rg = tid >> 5; // Rows / 16 row-groups
const int kl = tid & 31; // K lanes
const int64_t k_idx = k_base + kl;
const int64_t r0 = block_row + rg * 16;
const auto* src = operand + k_idx * ld + r0;
const bool aligned = (reinterpret_cast<uintptr_t>(src) & 15) == 0;
if (k_idx < contract && r0 + 15 < rows && aligned) {
const uint4 v = *reinterpret_cast<const uint4*>(src);
const auto* bytes = reinterpret_cast<const T8*>(&v);
// Scatter 16 bytes along the tile rows. The swizzle bit flips
// every 4 rows ((rg*16 + i) >> 2 & 1 == (i >> 2) & 1), and the
// physical column of row group g is kl ^ (16 * (g & 1)) — so the
// whole 16-byte scatter is one base pointer plus two alternating
// column offsets, no per-byte XOR in the address math.
// Operand stored [contract][rows]: contiguous along the non-contract
// dim. Each thread scatters one 16-byte run per K/32 pass; when the
// tile has more 16-row groups than warps (RowsTile > kThreads/2),
// each thread covers several groups.
constexpr int kWarpsTile = kThreads / 32;
constexpr int kGroups = RowsTile / 16;
static_assert(kGroups % kWarpsTile == 0,
"row groups must divide evenly across warps");
#pragma unroll
for (int g = 0; g < 4; ++g) {
T8* p = tile + (rg * 16 + 4 * g) * K
+ (g & 1 ? (kl ^ 16) : kl);
p[0] = bytes[4 * g];
p[K] = bytes[4 * g + 1];
p[2 * K] = bytes[4 * g + 2];
p[3 * K] = bytes[4 * g + 3];
}
} else {
// Predicated fallback: same layout, byte-granular gather.
const int col = kl;
for (int g = 0; g < kGroups / kWarpsTile; ++g) {
const int rg = (tid >> 5) + g * kWarpsTile;
const int kl = tid & 31; // byte column within a 32B pass
const int64_t r0 = block_row + rg * 16;
#pragma unroll
for (int g = 0; g < 4; ++g) {
const T8* src_g = operand + k_idx * ld + r0 + 4 * g;
T8* p = tile + (rg * 16 + 4 * g) * K
+ (g & 1 ? (col ^ 16) : col);
for (int pass = 0; pass < K / 32; ++pass) {
const int col = kl + pass * 32;
const int64_t k_idx = k_base + col;
const auto* src = operand + k_idx * ld + r0;
if (k_idx < contract && r0 + 15 < rows &&
(reinterpret_cast<uintptr_t>(src) & 15) == 0) {
const uint4 v = *reinterpret_cast<const uint4*>(src);
const auto* bytes = reinterpret_cast<const T8*>(&v);
// Scatter 16 bytes along the tile rows through tile_at's
// swizzle. Rows sharing a physical chunk form groups of
// (8 / kChunks) consecutive rows (see tile_at), so each
// group is one tile_at address plus a K-byte row stride.
constexpr int kGrp = 8 / kChunks;
#pragma unroll
for (int i = 0; i < 4; ++i) {
const int64_t r_idx = r0 + 4 * g + i;
p[i * K] = (r_idx < rows && k_idx < contract)
? src_g[i]
: T8(0.0f);
for (int j = 0; j < 16 / kGrp; ++j) {
T8* p = tile_at<K>(tile,
rg * 16 + j * kGrp, col);
#pragma unroll
for (int i = 0; i < kGrp; ++i)
p[i * K] = bytes[j * kGrp + i];
}
} else {
// Predicated fallback: same layout, byte-granular gather.
#pragma unroll
for (int i = 0; i < 16; ++i) {
const int64_t r_idx = r0 + i;
*tile_at<K>(tile, rg * 16 + i, col) =
(r_idx < rows && k_idx < contract)
? operand[k_idx * ld + r_idx]
: T8(0.0f);
}
}
}
}
} else {
// Operand stored [rows][contract]: contiguous along the contract dim.
const int r = tid >> 1;
const int c = (tid & 1) * 16;
const int64_t row = block_row + r;
// c is a multiple of 16, so the whole 16-byte run shares one chunk
// and dst[i] addressing below matches tile_at<K>(tile, r, c + i).
T8* dst = tile_at<K>(tile, r, c);
const auto* src = operand + row * ld + k_base + c;
const bool full = k_base + c + 15 < contract;
if (row < rows && full &&
(reinterpret_cast<uintptr_t>(src) & 15) == 0) {
astrai::cp_async_16(dst, src, true);
} else {
// Linear chunk mapping: thread covers kCpt consecutive 16B chunks of
// one row (K=64: a contiguous 32B pair; K=32: a single chunk).
const int r = tid / (kChunks / kCpt);
#pragma unroll
for (int i = 0; i < 16; ++i)
dst[i] = row < rows && k_base + c + i < contract ? src[i]
: T8(0.0f);
for (int j = 0; j < kCpt; ++j) {
const int c = ((tid % (kChunks / kCpt)) * kCpt + j) * 16;
const int64_t row = block_row + r;
const auto* src = operand + row * ld + k_base + c;
T8* dst = tile_at<K>(tile, r, c);
if (row < rows && k_base + c + 15 < contract &&
(reinterpret_cast<uintptr_t>(src) & 15) == 0) {
astrai::cp_async_16(dst, src, true);
} else {
#pragma unroll
for (int i = 0; i < 16; ++i)
dst[i] = row < rows && k_base + c + i < contract
? src[i]
: T8(0.0f);
}
}
}
}
@@ -222,13 +248,13 @@ __device__ __forceinline__ void load_operand_tile(
// ---------------------------------------------------------------------------
// Swizzled 16B-chunk address (tile_at's layout) as a raw shared-memory
// pointer for ldmatrix. Requires kK == 32 (2 chunks/row swizzle). The chunk
// XOR itself lives only in tile_at; this wrapper just converts the element
// address it returns.
// pointer for ldmatrix. Valid for kK in {32, 64} (the swizzle itself lives
// only in tile_at; this wrapper just converts the element address).
template <typename T8, int kK>
__device__ __forceinline__ unsigned frag_addr(const T8* tile, int row,
int chunk) {
static_assert(kK == 32, "fragment swizzle offsets assume kK == 32");
static_assert(kK == 32 || kK == 64,
"fragment swizzle offsets assume kK in {32, 64}");
return __cvta_generic_to_shared(tile_at<kK>(tile, row, chunk << 4));
}
@@ -241,13 +267,20 @@ __device__ __forceinline__ unsigned frag_addr(const T8* tile, int row,
// change how the stage-load gathers the operand from global memory:
// A ColMajor: tileA[m][p] = a[p*a_ld + m]; A RowMajor: a[m*a_ld + p]
// B RowMajor: tileB[n][p] = b[p*b_ld + n]; B ColMajor: b[n*b_ld + p]
// BlockM x BlockN CTA as (BlockM/64) x (BlockN/32) warps of 64x32 warp tiles
// (mt x nt = 4x4 MMA each). The 64x128 variant runs 4 warps / 128 threads and
// exists for small-M calls: m <= 64 wastes half of every 128-row CTA, so the
// launcher dispatches to it there (see launch_fp8_gemm).
template <typename Traits, bool OutFp8 = false, typename LayoutA = RowMajor, typename LayoutB = RowMajor>
__global__ void __launch_bounds__(kWarps * 32, 2) fp8_gemm_kernel(FP8Params p) {
__global__ void __launch_bounds__(
(Traits::kBlockM / 64) * (Traits::kBlockN / 32) * 32, 2)
fp8_gemm_kernel(FP8Params p) {
using T8 = std::conditional_t<Traits::kIsE5M2, __nv_fp8_e5m2, __nv_fp8_e4m3>;
constexpr int kBlockM = Traits::kBlockM;
constexpr int kBlockN = Traits::kBlockN;
constexpr int kK = Traits::kK;
constexpr int kStages = Traits::kStages;
constexpr int kCtaThreads = (kBlockM / 64) * (kBlockN / 32) * 32;
static_assert(kStages >= 1 && kStages <= 8,
"FP8 GEMM stages must be in the range [1, 8]");
// Tiles are flat [rows * kK] with a 16B-chunk XOR swizzle (tile_at):
@@ -269,13 +302,36 @@ __global__ void __launch_bounds__(kWarps * 32, 2) fp8_gemm_kernel(FP8Params p) {
const int lane = tid & 31;
const int group = lane >> 2;
const int thread_in_group = lane & 3;
// L2-friendly rasterization (CUTLASS-style grouped launch order): remap
// the linear block id so consecutive CTAs cover a group of kGroupM M-tiles
// before advancing along N. All CTAs of one group share the same B column
// stripe, so B tiles stay hot in L2 across the wave (the default
// N-fastest order makes each wave touch every B tile instead).
// Measured win for the A-crosswise layouts (10-21% at K>=2048) and loss
// for A-congruous (-17..20%, A's cp.async stream prefers the N-fastest
// order) — so the branch follows LayoutA.
constexpr int kGroupM = 8;
int block_m, block_n;
if constexpr (std::is_same_v<LayoutA, ColMajor>) {
const int blocks_m = gridDim.y;
const int bid = blockIdx.y * gridDim.x + blockIdx.x;
const int group_first_m = (bid / (kGroupM * gridDim.x)) * kGroupM;
const int group_rows =
min(blocks_m - group_first_m, kGroupM); // M-tail group is short
block_m = group_first_m + bid % group_rows;
block_n = (bid % (kGroupM * gridDim.x)) / group_rows;
} else {
block_m = blockIdx.y;
block_n = blockIdx.x;
}
// 128x128 CTA = 8 warps as 2x4 warp tiles of 64x32 (mt x nt = 4x4 MMA).
constexpr int warps_n = kBlockN / 32;
const int warp_m = warp / warps_n;
const int warp_n = warp % warps_n;
const int64_t row_base = blockIdx.y * kBlockM + warp_m * 64 + group;
const int64_t row_base =
(int64_t)block_m * kBlockM + warp_m * 64 + group;
const int64_t output_col =
blockIdx.x * kBlockN + warp_n * 32 + thread_in_group * 2;
(int64_t)block_n * kBlockN + warp_n * 32 + thread_in_group * 2;
const int a_row0 = warp_m * 64; // + mt * 16 in the loop
const int b_row0 = warp_n * 32; // + nt * 8
const float sa = *p.scale_a;
@@ -285,15 +341,17 @@ __global__ void __launch_bounds__(kWarps * 32, 2) fp8_gemm_kernel(FP8Params p) {
// Both operands are staged into the canonical [M][kK] / [N][kK] shared
// tiles regardless of their global layout (see load_operand_tile), so the
// MMA fragment reads below stay unchanged across the four layout
// combinations. Each 128x32 tile is 256 16B chunks: one per thread.
// A's tag already names the operand view ([M][K] = [rows][contract]);
// B's tag is relative to the canonical [K][N], so the stage-load sees its
// transpose (transpose_layout_t, see common.h).
// combinations. A's tag already names the operand view ([M][K] =
// [rows][contract]); B's tag is relative to the canonical [K][N], so the
// stage-load sees its transpose (transpose_layout_t, see common.h).
auto load_tile = [&](int stage, int64_t k_base) {
load_operand_tile<T8, kK, LayoutA>(
a_smem[stage], a, m, k, a_ld, tid, k_base, blockIdx.y * kBlockM);
load_operand_tile<T8, kK, transpose_layout_t<LayoutB>>(
b_smem[stage], b, n, k, b_ld, tid, k_base, blockIdx.x * kBlockN);
load_operand_tile<T8, kK, LayoutA, kBlockM, kCtaThreads>(
a_smem[stage], a, m, k, a_ld, tid, k_base,
(int64_t)block_m * kBlockM);
load_operand_tile<T8, kK, transpose_layout_t<LayoutB>, kBlockN,
kCtaThreads>(
b_smem[stage], b, n, k, b_ld, tid, k_base,
(int64_t)block_n * kBlockN);
};
const int64_t tile_count = (k + kK - 1) / kK;
@@ -339,15 +397,29 @@ __global__ void __launch_bounds__(kWarps * 32, 2) fp8_gemm_kernel(FP8Params p) {
// 4 ldmatrix.x2 (B) + 4 ldmatrix.x4 (A) feed 16 mma.sync per k_seg —
// 0.5 load instructions per MMA, versus 4.5 scalar LDS per MMA in
// the 128x64-tile version (the kernel was LSU-issue-bound there).
constexpr int kSegs = kK / kMmaK;
// B fragments double-buffered across k_segs: the next k_seg's B load
// is issued before the current k_seg's MMA sequence, so its LDS
// latency hides behind the A pipeline + tensor-pipe work (same trick
// as the A mt+1 prefetch below; costs kSegs x 8 registers).
unsigned b_frag[2][4][2];
#pragma unroll
for (int k_seg = 0; k_seg < kK / kMmaK; ++k_seg) {
unsigned b_frag[4][2];
for (int nt = 0; nt < 4; ++nt) {
const int row = b_row0 + nt * 8 + r7;
astrai::ldmatrix_x2_lane(b_frag[0][nt],
frag_addr<T8, kK>(b_smem[stage], row, rh8));
}
#pragma unroll
for (int nt = 0; nt < 4; ++nt) {
const int row = b_row0 + nt * 8 + r7;
astrai::ldmatrix_x2_lane(b_frag[nt],
frag_addr<T8, kK>(b_smem[stage], row,
k_seg * 2 + rh8));
for (int k_seg = 0; k_seg < kSegs; ++k_seg) {
const int bcur = k_seg & 1, bnext = bcur ^ 1;
if (k_seg + 1 < kSegs) {
#pragma unroll
for (int nt = 0; nt < 4; ++nt) {
const int row = b_row0 + nt * 8 + r7;
astrai::ldmatrix_x2_lane(b_frag[bnext][nt],
frag_addr<T8, kK>(b_smem[stage], row,
(k_seg + 1) * 2 + rh8));
}
}
// Software-pipelined A fragments: the ldmatrix.x4 for row mt+1
// is issued before the MMAs consuming row mt, so the LDS fixed
@@ -367,8 +439,8 @@ __global__ void __launch_bounds__(kWarps * 32, 2) fp8_gemm_kernel(FP8Params p) {
k_seg * 2 + rh16));
#pragma unroll
for (int nt = 0; nt < 4; ++nt)
astrai::mma_sync<T8>(acc[nt][mt], a_frag[mt], b_frag[nt],
acc[nt][mt]);
astrai::mma_sync<T8>(acc[nt][mt], a_frag[mt],
b_frag[bcur][nt], acc[nt][mt]);
}
}
// Barrier 2: every thread finished reading this stage's tiles before
@@ -440,18 +512,27 @@ void launch_fp8_quantize(const FP8Params& p, cudaStream_t stream) {
fp8_quantize_kernel<Fmt><<<blocks, kThreads, 0, stream>>>(p);
}
// Pre-quantized GEMM tile config: 128x128 CTA (8 warps x 64x32 warp tiles),
// K=32, 3-stage pipeline (24KB smem -> 2 CTAs/SM). The wide warp tile plus
// ldmatrix fragments lifts the LSU-issue bound of the old 128x64 config.
// Stages remains an explicit template override for tuning. LayoutA/LayoutB
// mirror the kernel template (defaults keep the NN layout: out = a @ b).
// Pre-quantized GEMM tile config: 128x128 CTA (8 warps x 64x32 warp tiles).
// kK selects the K tile (32 or 64; 64 halves the __syncthreads count per K
// and doubles the MMA work per stage, at 2x the smem per stage — measured
// 10-35% across shapes, so 64 is the default). Stages=2 with kK=64 keeps the
// pipeline at 32KB smem; deeper pipelines only win on K >= 4096 squares and
// lose elsewhere. LayoutA/LayoutB mirror the kernel template (defaults keep
// the NN layout: out = a @ b). m <= 64 dispatches to the 64x128 CTA — a
// 128-row CTA would waste half its MMA work on predicated-off rows.
template <FP8Format Fmt, bool OutFp8 = false, typename LayoutA = RowMajor,
typename LayoutB = RowMajor, int Stages = 3>
typename LayoutB = RowMajor, int kK = 64, int Stages = 2>
void launch_fp8_gemm(const FP8Params& p, cudaStream_t stream) {
using Traits = Fp8GemmTraits<Fmt, 128, 128, 32, Stages>;
dim3 grid((p.n + Traits::kBlockN - 1) / Traits::kBlockN,
(p.m + Traits::kBlockM - 1) / Traits::kBlockM);
fp8_gemm_kernel<Traits, OutFp8, LayoutA, LayoutB><<<grid, kWarps * 32, 0, stream>>>(p);
dim3 grid((p.n + 127) / 128, (p.m + 127) / 128);
if (p.m <= 64) {
using Traits = Fp8GemmTraits<Fmt, 64, 128, kK, Stages>;
fp8_gemm_kernel<Traits, OutFp8, LayoutA, LayoutB>
<<<grid, (64 / 64) * (128 / 32) * 32, 0, stream>>>(p);
} else {
using Traits = Fp8GemmTraits<Fmt, 128, 128, kK, Stages>;
fp8_gemm_kernel<Traits, OutFp8, LayoutA, LayoutB>
<<<grid, (128 / 64) * (128 / 32) * 32, 0, stream>>>(p);
}
}
} // namespace fp8