refactor: reorganize CUDA kernels into per-family directories
- move attention kernels to csrc/kernels/attention/ and rotary to rotary/ - add shared common/mma.cuh (mma_sync, ldmatrix) and device.cuh (sm checks) - split fp8_mm into three-layer fp8/common.h, gemm.cuh, mm.cu - fix fused FP8 GEMM ldmatrix lane indexing to fix OOB shared reads - update extension ops, loader, and kernel tests
This commit is contained in:
@@ -0,0 +1,369 @@
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// FP8 GEMM torch binding: tensor validation, FP8Params packing, template
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// dispatch and pybind. Device code lives in gemm.cuh (pure CUDA) —
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// mirroring the attn_*.cu / attn_*_mma.cuh split of the attention kernels.
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#include <torch/extension.h>
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#include <ATen/cuda/CUDAContext.h>
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#include <c10/cuda/CUDAGuard.h>
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#include <cuda_bf16.h>
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#include <cstdint>
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#include <mutex>
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#include <tuple>
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#include <unordered_map>
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#include "gemm.cuh"
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#include "../common/device.cuh"
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namespace {
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// FP8Format / FP8Params live in the global namespace (common.h); the
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// launchers live in fp8:: (gemm.cuh).
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void check_fp8_device(const torch::Tensor& tensor) {
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static std::mutex mutex;
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static std::unordered_map<int, bool> supported;
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const int device = tensor.device().index();
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{
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std::lock_guard<std::mutex> lock(mutex);
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auto cached = supported.find(device);
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if (cached != supported.end()) {
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TORCH_CHECK(cached->second,
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"fused FP8 MMA requires compute capability 8.9 or newer");
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return;
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}
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}
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const auto* properties = at::cuda::getDeviceProperties(device);
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const bool is_supported =
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astrai::sm_at_least(properties->major, properties->minor,
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astrai::kMinSmForFp8Major,
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astrai::kMinSmForFp8Minor);
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{
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std::lock_guard<std::mutex> lock(mutex);
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supported.emplace(device, is_supported);
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}
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TORCH_CHECK(is_supported,
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"fused FP8 MMA requires compute capability 8.9 or newer");
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}
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void check_scale(const torch::Tensor& scale, const torch::Tensor& input,
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const char* name) {
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TORCH_CHECK(scale.is_cuda() && scale.device() == input.device() &&
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scale.scalar_type() == torch::kFloat32 && scale.numel() == 1,
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name, " must be a CUDA float32 scalar on the input device");
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}
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// ---- FP8Params packing (mirrors attention/entry_utils.cuh pack_* helpers) ----
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void pack_gemm_params(FP8Params& p, const void* a, const void* b, void* out,
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const torch::Tensor& sa, const torch::Tensor& sb,
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const torch::Tensor* out_scale, int64_t m, int64_t n,
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int64_t k) {
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p.a_ptr = a;
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p.b_ptr = b;
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p.out_ptr = out;
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p.scale_a = sa.data_ptr<float>();
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p.scale_b = sb.data_ptr<float>();
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p.out_scale = out_scale ? out_scale->data_ptr<float>() : nullptr;
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p.bias = nullptr;
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p.amax_a = nullptr;
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p.amax_b = nullptr;
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p.m = m;
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p.n = n;
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p.k = k;
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p.total = 0;
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}
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void pack_quantize_params(FP8Params& p, const void* x, void* x8,
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const torch::Tensor& scale, torch::Tensor* amax,
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int64_t total) {
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p.a_ptr = x;
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p.b_ptr = nullptr;
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p.out_ptr = x8;
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p.scale_a = scale.data_ptr<float>();
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p.scale_b = nullptr;
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p.out_scale = nullptr;
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p.bias = nullptr;
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p.amax_a = amax ? amax->data_ptr<float>() : nullptr;
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p.amax_b = nullptr;
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p.m = p.n = p.k = 0;
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p.total = total;
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}
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} // namespace
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// ---------------------------------------------------------------------------
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// Entry points
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// ---------------------------------------------------------------------------
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std::tuple<torch::Tensor, torch::Tensor> quantize_bf16(torch::Tensor x,
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torch::Tensor scale,
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int64_t fmt) {
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// BF16 -> FP8 quantize with fused amax. fmt: 0 = E4M3, 1 = E5M2.
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// Returns (x8, amax); the caller never clears amax (zero-initialized here).
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TORCH_CHECK(x.is_cuda() && scale.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(x.scalar_type() == torch::kBFloat16, "x must be bf16");
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check_scale(scale, x, "scale");
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check_fp8_device(x);
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const at::cuda::OptionalCUDAGuard guard(x.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto x_c = x.contiguous();
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auto x8 = torch::empty_like(
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x_c, x_c.options().dtype(fmt ? torch::kFloat8_e5m2
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: torch::kFloat8_e4m3fn));
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auto amax = torch::zeros({1}, x_c.options().dtype(torch::kFloat32));
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FP8Params p;
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pack_quantize_params(p, x_c.data_ptr(), x8.data_ptr(), scale, &amax,
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x_c.numel());
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if (fmt) {
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fp8::launch_fp8_quantize<FP8Format::E5M2>(p, stream.stream());
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} else {
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fp8::launch_fp8_quantize<FP8Format::E4M3>(p, stream.stream());
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}
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C10_CUDA_CHECK(cudaGetLastError());
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return {x8, amax};
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}
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torch::Tensor mm_fp8(torch::Tensor a, torch::Tensor b, torch::Tensor sa,
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torch::Tensor sb, int64_t out_dtype,
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c10::optional<torch::Tensor> out_scale) {
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// Pre-quantized FP8 GEMM: out = a @ b^T * (sa * sb), FP32 accumulation.
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// out_dtype: 0 = BF16 (default), 1 = FP8 E4M3 (requires out_scale, the
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// quantization step for the output — mirrors torch._scaled_mm's
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// out_dtype / scale_result). Both operands share the same FP8 format.
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TORCH_CHECK(a.is_cuda() && b.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(a.scalar_type() == torch::kFloat8_e4m3fn ||
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a.scalar_type() == torch::kFloat8_e5m2,
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"a and b must be fp8 (e4m3fn or e5m2)");
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TORCH_CHECK(a.scalar_type() == b.scalar_type(),
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"a and b must share the same fp8 format");
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TORCH_CHECK(a.dim() == 2 && b.dim() == 2, "a and b must be 2D");
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TORCH_CHECK(a.device() == b.device(), "a and b must be on the same device");
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TORCH_CHECK(a.size(1) == b.size(1), "inner dim mismatch");
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check_scale(sa, a, "sa");
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check_scale(sb, a, "sb");
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check_fp8_device(a);
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const at::cuda::OptionalCUDAGuard guard(a.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto a_c = a.contiguous();
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auto b_c = b.contiguous();
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int64_t m = a_c.size(0), k = a_c.size(1), n = b_c.size(0);
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const bool out_fp8 = (out_dtype == 1);
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TORCH_CHECK(out_dtype == 0 || out_fp8,
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"out_dtype must be 0 (bf16) or 1 (fp8 e4m3)");
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torch::Tensor os;
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if (out_fp8) {
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TORCH_CHECK(out_scale.has_value(), "fp8 output requires out_scale");
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os = out_scale.value();
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check_scale(os, a, "out_scale");
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}
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auto out = torch::empty(
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{m, n},
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out_fp8 ? a_c.options().dtype(torch::kFloat8_e4m3fn)
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: a_c.options().dtype(torch::kBFloat16));
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FP8Params p;
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pack_gemm_params(p, a_c.data_ptr(), b_c.data_ptr(), out.data_ptr(), sa, sb,
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out_fp8 ? &os : nullptr, m, n, k);
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if (a.scalar_type() == torch::kFloat8_e4m3fn) {
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if (out_fp8) {
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fp8::launch_fp8_pq<FP8Format::E4M3, true>(p, stream.stream());
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} else {
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fp8::launch_fp8_pq<FP8Format::E4M3>(p, stream.stream());
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}
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} else {
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if (out_fp8) {
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fp8::launch_fp8_pq<FP8Format::E5M2, true>(p, stream.stream());
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} else {
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fp8::launch_fp8_pq<FP8Format::E5M2>(p, stream.stream());
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}
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}
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C10_CUDA_CHECK(cudaGetLastError());
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return out;
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}
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std::tuple<torch::Tensor, torch::Tensor, torch::Tensor> linear_forward_fp8(
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torch::Tensor x, torch::Tensor w, torch::Tensor bias, torch::Tensor sx,
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torch::Tensor sw) {
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// Fused BF16 -> E4M3 -> MMA -> BF16 linear forward. amax_x / amax_w are
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// zero-initialized here and returned (caller does not clear them).
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TORCH_CHECK(x.is_cuda() && w.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(x.scalar_type() == torch::kBFloat16 &&
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w.scalar_type() == torch::kBFloat16,
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"x and w must be bf16");
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TORCH_CHECK(x.device() == w.device(), "x and w must be on the same device");
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check_scale(sx, x, "sx");
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check_scale(sw, x, "sw");
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check_fp8_device(x);
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const at::cuda::OptionalCUDAGuard guard(x.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto x_c = x.reshape({-1, w.size(1)}).contiguous();
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auto w_c = w.contiguous();
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int64_t m = x_c.size(0), k = x_c.size(1), n = w_c.size(0);
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TORCH_CHECK(w_c.dim() == 2 && w_c.size(1) == k, "inner dim mismatch");
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// amax slots are zero-initialized here; the kernel atomically maxes in.
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auto amax_x = torch::zeros({1}, x.options().dtype(torch::kFloat32));
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auto amax_w = torch::zeros({1}, x.options().dtype(torch::kFloat32));
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auto out = torch::empty({m, n}, x_c.options());
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const bool has_bias = bias.defined() && bias.numel() > 0;
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if (has_bias) {
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TORCH_CHECK(bias.is_cuda() && bias.device() == x.device() &&
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bias.scalar_type() == torch::kBFloat16 &&
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bias.numel() == n,
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"bias must be CUDA bf16 with shape [N]");
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}
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FP8Params p;
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pack_gemm_params(p, x_c.data_ptr(), w_c.data_ptr(), out.data_ptr(), sx, sw,
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nullptr, m, n, k);
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p.bias = has_bias ? reinterpret_cast<const __nv_bfloat16*>(bias.data_ptr())
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: nullptr;
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p.amax_a = amax_x.data_ptr<float>();
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p.amax_b = amax_w.data_ptr<float>();
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if (has_bias) {
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fp8::launch_fp8_fused<true, true>(p, stream.stream());
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} else {
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fp8::launch_fp8_fused<false, true>(p, stream.stream());
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}
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C10_CUDA_CHECK(cudaGetLastError());
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std::vector<int64_t> shape(x.sizes().begin(), x.sizes().end() - 1);
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shape.push_back(n);
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return {out.reshape(shape), amax_x, amax_w};
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}
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std::tuple<torch::Tensor, torch::Tensor, torch::Tensor, torch::Tensor>
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linear_backward_fp8(torch::Tensor g, torch::Tensor x, torch::Tensor w,
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std::vector<int64_t> masks, torch::Tensor sg,
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torch::Tensor sw, torch::Tensor sx, int64_t fmt) {
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// Pre-quantized FP8 backward: grad is quantized once (E4M3 or E5M2 per
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// `fmt`), then dX / dW run as FP8 tensor-core GEMMs sharing g8.
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// Returns (grad_input, grad_weight, grad_bias, amax_g).
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TORCH_CHECK(g.is_cuda() && x.is_cuda() && w.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(g.scalar_type() == torch::kBFloat16 &&
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x.scalar_type() == torch::kBFloat16 &&
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w.scalar_type() == torch::kBFloat16,
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"g, x, and w must be bf16");
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TORCH_CHECK(g.device() == x.device() && g.device() == w.device(),
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"g, x, and w must be on the same device");
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TORCH_CHECK(masks.size() == 3, "masks must contain three values");
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check_fp8_device(g);
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const at::cuda::OptionalCUDAGuard guard(g.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto g_c = g.reshape({-1, w.size(0)}).contiguous(); // [M, N]
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auto x_c = x.reshape({-1, x.size(-1)}).contiguous(); // [M, K]
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auto w_c = w.contiguous(); // [N, K]
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int64_t m = g_c.size(0), n = w_c.size(0), k = w_c.size(1);
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TORCH_CHECK(x_c.size(0) == m && x_c.size(1) == k && g_c.size(1) == n,
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"backward shape mismatch");
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auto grad_input = torch::empty_like(x);
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auto grad_weight = torch::empty_like(w);
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auto grad_bias = torch::empty({0}, g.options());
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auto amax_g = torch::zeros({1}, g.options().dtype(torch::kFloat32));
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auto f8opt = fmt ? g.options().dtype(torch::kFloat8_e5m2)
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: g.options().dtype(torch::kFloat8_e4m3fn);
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const auto q_fmt = fmt ? FP8Format::E5M2 : FP8Format::E4M3;
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auto quantize = [&](const torch::Tensor& src, torch::Tensor& dst,
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const torch::Tensor& scale, torch::Tensor* amax) {
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FP8Params qp;
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pack_quantize_params(qp, src.data_ptr(), dst.data_ptr(), scale, amax,
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src.numel());
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if (fmt) {
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fp8::launch_fp8_quantize<FP8Format::E5M2>(qp, stream.stream());
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} else {
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fp8::launch_fp8_quantize<FP8Format::E4M3>(qp, stream.stream());
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}
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};
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auto pq = [&](const torch::Tensor& a8, const torch::Tensor& b8,
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torch::Tensor& out, const torch::Tensor& sa,
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const torch::Tensor& sb, int64_t mm, int64_t nn, int64_t kk) {
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FP8Params gp;
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pack_gemm_params(gp, a8.data_ptr(), b8.data_ptr(), out.data_ptr(), sa,
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sb, nullptr, mm, nn, kk);
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if (fmt) {
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fp8::launch_fp8_pq<FP8Format::E5M2>(gp, stream.stream());
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} else {
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fp8::launch_fp8_pq<FP8Format::E4M3>(gp, stream.stream());
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}
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};
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// dX = g @ W: quantize g once, then g8 @ w8^T.
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if (masks[0]) {
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auto g8 = torch::empty({m, n}, f8opt);
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quantize(g_c, g8, sg, &amax_g);
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auto w_t = w_c.transpose(0, 1).contiguous(); // [K, N]
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auto w8_t = torch::empty({k, n}, f8opt);
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quantize(w_t, w8_t, sw, nullptr);
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auto grad_input_2d = grad_input.reshape({m, k});
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pq(g8, w8_t, grad_input_2d, sg, sw, m, k, n);
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}
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// dW = g^T @ x: transposed layouts for both operands.
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if (masks[1]) {
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auto g_t = g_c.transpose(0, 1).contiguous(); // [N, M]
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auto x_t = x_c.transpose(0, 1).contiguous(); // [K, M]
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auto g8_t = torch::empty({n, m}, f8opt);
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auto x8_t = torch::empty({k, m}, f8opt);
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quantize(g_t, g8_t, sg, nullptr);
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quantize(x_t, x8_t, sx, nullptr);
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pq(g8_t, x8_t, grad_weight, sg, sx, n, k, m);
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}
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if (!masks[0] && !masks[1]) {
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amax_g.copy_(g_c.abs().amax().to(torch::kFloat32));
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}
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C10_CUDA_CHECK(cudaGetLastError());
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if (masks[2]) grad_bias = g_c.sum(0).to(g.scalar_type());
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return {grad_input, grad_weight, grad_bias, amax_g};
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}
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torch::Tensor fp8_mm(torch::Tensor a, torch::Tensor b, torch::Tensor sx,
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torch::Tensor sw) {
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// BF16-in fused FP8 GEMM primitive (no bias, no amax): a @ b^T.
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TORCH_CHECK(a.is_cuda() && b.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(a.scalar_type() == torch::kBFloat16 &&
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b.scalar_type() == torch::kBFloat16,
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"a and b must be bf16");
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TORCH_CHECK(a.dim() == 2 && b.dim() == 2, "a and b must be 2D");
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TORCH_CHECK(a.device() == b.device(), "a and b must be on the same device");
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TORCH_CHECK(a.size(1) == b.size(1), "inner dim mismatch");
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check_scale(sx, a, "sx");
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check_scale(sw, a, "sw");
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check_fp8_device(a);
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const at::cuda::OptionalCUDAGuard guard(a.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto a_c = a.contiguous();
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auto b_c = b.contiguous();
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int64_t m = a_c.size(0), n = b_c.size(0), k = a_c.size(1);
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auto out = torch::empty({m, n}, a_c.options());
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FP8Params p;
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pack_gemm_params(p, a_c.data_ptr(), b_c.data_ptr(), out.data_ptr(), sx, sw,
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nullptr, m, n, k);
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fp8::launch_fp8_fused<false, false>(p, stream.stream());
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C10_CUDA_CHECK(cudaGetLastError());
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return out;
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}
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PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
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m.def("fp8_mm", &fp8_mm, py::arg("a"), py::arg("b"), py::arg("sx"),
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py::arg("sw"),
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"Fused BF16 input, E4M3 MMA, FP32 accumulation, BF16 output GEMM");
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m.def("quantize_bf16", &quantize_bf16, py::arg("x"), py::arg("scale"),
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py::arg("fmt"),
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||||
"BF16 to FP8 (E4M3/E5M2) quantize with fused amax; returns (x8, amax)");
|
||||
m.def("mm_fp8", &mm_fp8, py::arg("a"), py::arg("b"), py::arg("sa"),
|
||||
py::arg("sb"), py::arg("out_dtype") = 0,
|
||||
py::arg("out_scale") = py::none(),
|
||||
"Pre-quantized FP8 GEMM: a @ b^T * (sa * sb); out_dtype 0=bf16, "
|
||||
"1=fp8 e4m3 (requires out_scale)");
|
||||
m.def("linear_forward_fp8", &linear_forward_fp8, py::arg("x"),
|
||||
py::arg("w"), py::arg("bias"), py::arg("sx"), py::arg("sw"),
|
||||
"Fused BF16-to-FP8 linear forward; returns (out, amax_x, amax_w)");
|
||||
m.def("linear_backward_fp8", &linear_backward_fp8, py::arg("g"),
|
||||
py::arg("x"), py::arg("w"), py::arg("masks"), py::arg("sg"),
|
||||
py::arg("sw"), py::arg("sx"), py::arg("fmt"),
|
||||
"FP8 linear backward; returns (grad_input, grad_weight, grad_bias, amax_g)");
|
||||
}
|
||||
Reference in New Issue
Block a user