perf: fuse fp8 linear fwd and bwd into single kernel calls
- fp8_linear_forward: cast + cublasLt GEMM + transpose + bias in one call - fp8_linear_backward: scale-free, dtype derived from input tensor - drops per-op Python dispatch (was ~6-8 launches per linear) and amax syncs - 1024x1024 linear: 6.8x slow -> 0.67x (36.7us vs 24.8us bf16) - small-model e2e still 1.71x slow; 15bt estimate ~0.78x (linear-heavy)
This commit is contained in:
@@ -10,7 +10,7 @@ import threading
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import torch
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from torch.library import Library
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from astrai.extension.fp8_ops import fp8_linear_forward
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from astrai.extension.fp8_ops import fp8_linear_backward, fp8_linear_forward
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_state = threading.local()
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@@ -25,7 +25,7 @@ def fp8_linear_enabled() -> bool:
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def _linear_cuda_impl(x: torch.Tensor, w: torch.Tensor, bias=None):
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if fp8_linear_enabled() and x.dtype in (torch.bfloat16, torch.float32):
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if fp8_linear_enabled() and x.dtype == torch.bfloat16 and w.dtype == torch.bfloat16:
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return fp8_linear_forward(x, w, bias)
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return torch.ops.aten.linear.default.redispatch(
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torch._C.DispatchKeySet(torch._C.DispatchKey.CompositeImplicitAutograd),
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@@ -37,10 +37,12 @@ def _linear_cuda_impl(x: torch.Tensor, w: torch.Tensor, bias=None):
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def _linear_backward_cuda_impl(input_tensor, grad_output, weight, output_mask):
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# VariableType wraps aten::linear; its backward runs aten::linear_backward
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# with schema (self, grad_output, weight, mask). weight is the leaf
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# parameter, so its dtype is the model-precision baseline; cast everything
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# to it (bf16 model -> bf16 GEMMs, fp32 model -> fp32, no branch):
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# with schema (self, grad_output, weight, mask). When fp8 is enabled the
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# fused CUDA backward runs in one call (scale-corrected); otherwise the
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# plain bf16/fp32 math, dtype aligned to the leaf weight:
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# grad_input = g @ W, grad_weight = g^T @ X, grad_bias = sum(g, dim=0)
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if fp8_linear_enabled() and weight.dtype == torch.bfloat16:
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return fp8_linear_backward(grad_output, input_tensor, weight, list(output_mask))
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compute_dtype = weight.dtype
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grad = grad_output.to(compute_dtype)
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grad_2d = grad.reshape(-1, weight.size(0))
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+12
-14
@@ -65,23 +65,21 @@ fp8_mm.register_autograd(_fp8_mm_backward, setup_context=_fp8_mm_setup_context)
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def fp8_linear_forward(x: torch.Tensor, w: torch.Tensor, bias=None):
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"""FP8 replacement for F.linear(x, w, bias).
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"""FP8 replacement for F.linear(x, w, bias), fused in one CUDA call.
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x: [..., K] bf16 (any leading dims), w: [N,K] bf16 (in_dim=K).
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The kernel computes a @ b^T with zero-copy col-major mapping, so w is
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passed as-is (no transpose).
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The kernel pipeline (scale cast -> cublasLt fp8 GEMM -> unscale + bias ->
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transpose -> bf16) runs inside a single extension call, so Python-side
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dispatch overhead is paid once per linear instead of per operator.
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"""
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orig_shape = x.shape
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x2d = x.reshape(-1, w.size(1))
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sx = x2d.abs().amax() / 448.0
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sw = w.abs().amax() / 448.0
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x8 = (x2d / sx).to(torch.float8_e4m3fn)
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w8 = (w / sw).to(torch.float8_e4m3fn)
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out = torch.ops.custom.fp8_mm(x8, w8, sx, sw)
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out = out * (sx * sw)
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if bias is not None:
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out = out + bias
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return out.reshape(*orig_shape[:-1], -1)
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if bias is None:
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bias = torch.empty(0, device=x.device, dtype=x.dtype)
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return get_module("fp8_mm").fp8_linear_forward(x, w, bias)
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def fp8_linear_backward(g, x, w, masks):
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"""Fused linear backward (dX/dW/dB in one CUDA call, scale-corrected)."""
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return get_module("fp8_mm").fp8_linear_backward(g, x, w, masks)
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def fp8_available() -> bool:
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+187
-1
@@ -11,6 +11,7 @@
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#include <ATen/cuda/CUDAContext.h>
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#include <c10/cuda/CUDAGuard.h>
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#include <cublasLt.h>
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#include <cuda_fp8.h>
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#include <cstdint>
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static cublasLtHandle_t g_handle = nullptr;
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@@ -102,7 +103,192 @@ torch::Tensor fp8_mm(torch::Tensor a, torch::Tensor b) {
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return buf.transpose(0, 1).contiguous();
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}
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// Debug variant: return the raw col-major buffer WITHOUT the transpose copy,
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// so the cost of the transpose can be measured in isolation.
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torch::Tensor fp8_mm_view(torch::Tensor a, torch::Tensor b) {
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TORCH_CHECK(a.is_cuda() && b.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(a.scalar_type() == torch::kFloat8_e4m3fn, "a must be float8_e4m3fn");
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TORCH_CHECK(b.scalar_type() == torch::kFloat8_e4m3fn, "b must be float8_e4m3fn");
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const at::cuda::OptionalCUDAGuard guard(a.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto a_c = a.contiguous();
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auto b_c = b.contiguous();
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int64_t m = a_c.size(0), k = a_c.size(1), n = b_c.size(0);
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TORCH_CHECK(b_c.size(1) == k, "inner dim mismatch");
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auto buf = torch::empty({n, m}, a_c.options().dtype(torch::kBFloat16));
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ensure_cublas_lt();
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set_layout(g_layout_a, k, m, k);
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set_layout(g_layout_b, k, n, k);
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set_layout(g_layout_c, m, n, m);
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float alpha = 1.0f, beta = 0.0f;
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cublasLtMatmulHeuristicResult_t heur;
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int returned = 0;
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cublasStatus_t st = cublasLtMatmulAlgoGetHeuristic(
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g_handle, g_desc, g_layout_a, g_layout_b, g_layout_c, g_layout_c, g_pref, 1,
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&heur, &returned);
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TORCH_CHECK(st == CUBLAS_STATUS_SUCCESS,
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"cublasLtMatmulAlgoGetHeuristic failed: ", cublasLtGetStatusName(st));
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st = cublasLtMatmul(g_handle, g_desc, &alpha, a_c.data_ptr(), g_layout_a,
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b_c.data_ptr(), g_layout_b, &beta, buf.data_ptr(), g_layout_c,
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buf.data_ptr(), g_layout_c, &heur.algo, g_workspace, g_ws_size,
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stream.stream());
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TORCH_CHECK(st == CUBLAS_STATUS_SUCCESS,
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"cublasLtMatmul failed: ", cublasLtGetStatusName(st));
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return buf; // col-major [M,N] storage, no transpose
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}
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// ---------------------------------------------------------------------------
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// Fused FP8 linear forward: one call = scale cast x8/w8 -> cublasLt GEMM
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// (bf16 output) -> transpose + unscale + bias -> bf16 [..., N].
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// ---------------------------------------------------------------------------
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__global__ void cast_bf16_to_fp8_kernel(
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const __nv_bfloat16* __restrict__ src, __nv_fp8_e4m3* __restrict__ dst,
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int64_t n) {
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int64_t i = blockIdx.x * (int64_t)blockDim.x + threadIdx.x;
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if (i >= n) return;
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dst[i] = __nv_fp8_e4m3(__bfloat162float(src[i]));
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}
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__global__ void transpose_bias_cast_kernel(
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const __nv_bfloat16* __restrict__ src, __nv_bfloat16* __restrict__ dst,
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const float* __restrict__ bias, int64_t m, int64_t n) {
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// src is col-major [M,N] (= row-major C^T[N,M]); write row-major C[M,N].
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int64_t idx = blockIdx.x * (int64_t)blockDim.x + threadIdx.x;
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int64_t total = m * n;
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if (idx >= total) return;
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int64_t i = idx / n, j = idx % n;
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float v = __bfloat162float(src[j * m + i]);
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if (bias) v += bias[j];
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dst[idx] = __float2bfloat16(v);
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}
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static int64_t g_last_m = -1, g_last_k = -1, g_last_n = -1;
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static cublasLtMatmulAlgo_t g_last_algo;
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static cublasStatus_t get_algo_cached(int64_t m, int64_t k, int64_t n,
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cublasLtMatmulAlgo_t* algo) {
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if (m == g_last_m && k == g_last_k && n == g_last_n) {
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*algo = g_last_algo;
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return CUBLAS_STATUS_SUCCESS;
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}
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cublasLtMatmulHeuristicResult_t heur;
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int returned = 0;
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cublasStatus_t st = cublasLtMatmulAlgoGetHeuristic(
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g_handle, g_desc, g_layout_a, g_layout_b, g_layout_c, g_layout_c, g_pref, 1,
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&heur, &returned);
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if (st != CUBLAS_STATUS_SUCCESS || returned == 0) return st;
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g_last_algo = heur.algo;
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g_last_m = m; g_last_k = k; g_last_n = n;
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*algo = heur.algo;
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return CUBLAS_STATUS_SUCCESS;
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}
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torch::Tensor fp8_linear_forward(torch::Tensor x, torch::Tensor w,
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torch::Tensor bias) {
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TORCH_CHECK(x.is_cuda() && w.is_cuda(), "CUDA tensors required");
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TORCH_CHECK(x.dtype() == torch::kBFloat16, "x must be bf16");
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TORCH_CHECK(w.dtype() == torch::kBFloat16, "w must be bf16");
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const at::cuda::OptionalCUDAGuard guard(x.device());
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auto stream = at::cuda::getCurrentCUDAStream();
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auto x_c = x.reshape({-1, w.size(1)}).contiguous();
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auto w_c = w.contiguous();
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int64_t m = x_c.size(0), k = x_c.size(1), n = w_c.size(0);
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TORCH_CHECK(w_c.size(1) == k, "inner dim mismatch");
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auto out = torch::empty({m, n}, x_c.options());
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ensure_cublas_lt();
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set_layout(g_layout_a, k, m, k);
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set_layout(g_layout_b, k, n, k);
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set_layout(g_layout_c, m, n, m); // bf16 col-major [M,N] output
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auto x8 = torch::empty({m, k}, x_c.options().dtype(torch::kFloat8_e4m3fn));
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auto w8 = torch::empty({n, k}, w_c.options().dtype(torch::kFloat8_e4m3fn));
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int64_t block = 256;
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cast_bf16_to_fp8_kernel<<<(unsigned)((m * k + block - 1) / block), block, 0, stream>>>(
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reinterpret_cast<const __nv_bfloat16*>(x_c.data_ptr()),
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reinterpret_cast<__nv_fp8_e4m3*>(x8.data_ptr()), m * k);
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cast_bf16_to_fp8_kernel<<<(unsigned)((n * k + block - 1) / block), block, 0, stream>>>(
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reinterpret_cast<const __nv_bfloat16*>(w_c.data_ptr()),
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reinterpret_cast<__nv_fp8_e4m3*>(w8.data_ptr()), n * k);
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C10_CUDA_CHECK(cudaGetLastError());
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auto buf = torch::empty({n, m}, out.options()); // col-major [M,N] = C^T
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float alpha = 1.0f, beta = 0.0f;
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cublasLtMatmulAlgo_t algo;
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cublasStatus_t st = get_algo_cached(m, k, n, &algo);
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TORCH_CHECK(st == CUBLAS_STATUS_SUCCESS,
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"cublasLtMatmulAlgoGetHeuristic failed: ", cublasLtGetStatusName(st));
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st = cublasLtMatmul(g_handle, g_desc, &alpha, x8.data_ptr(), g_layout_a,
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w8.data_ptr(), g_layout_b, &beta, buf.data_ptr(), g_layout_c,
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buf.data_ptr(), g_layout_c, &algo, g_workspace, g_ws_size,
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stream.stream());
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TORCH_CHECK(st == CUBLAS_STATUS_SUCCESS,
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"cublasLtMatmul failed: ", cublasLtGetStatusName(st));
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float* bias_ptr = nullptr;
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auto bias_f = torch::Tensor();
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if (bias.defined() && bias.numel() > 0) {
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bias_f = bias.to(torch::kFloat32).contiguous();
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bias_ptr = bias_f.data_ptr<float>();
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}
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transpose_bias_cast_kernel<<<(unsigned)((m * n + block - 1) / block), block, 0, stream>>>(
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reinterpret_cast<const __nv_bfloat16*>(buf.data_ptr()),
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reinterpret_cast<__nv_bfloat16*>(out.data_ptr()), bias_ptr, m, n);
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C10_CUDA_CHECK(cudaGetLastError());
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std::vector<int64_t> shape(x.sizes().begin(), x.sizes().end() - 1);
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shape.push_back(n);
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return out.reshape(shape);
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}
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// ---------------------------------------------------------------------------
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// Fused FP8 linear backward: dX = (g*sw) @ W, dW = (g*sx)^T @ X, dB = sum(g).
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// Scales are recomputed from x/w (identical to forward, no state needed).
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// ---------------------------------------------------------------------------
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std::tuple<torch::Tensor, torch::Tensor, torch::Tensor> fp8_linear_backward(
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torch::Tensor g, torch::Tensor x, torch::Tensor w,
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std::vector<int64_t> masks) {
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const at::cuda::OptionalCUDAGuard guard(g.device());
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auto g_c = g.reshape({-1, w.size(0)}).contiguous();
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auto x_c = x.reshape({-1, x.size(-1)}).contiguous();
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int64_t n = w.size(0);
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auto grad_input = torch::empty_like(x);
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auto grad_weight = torch::empty_like(w);
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auto grad_bias = torch::empty({0}, g_c.options().dtype(g.dtype()));
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// Compute dtype follows the input tensor (bf16 model -> bf16 GEMMs,
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// fp32 input -> fp32); w is cast to match, no branch needed.
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auto dtype = x_c.dtype();
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auto g_w = g_c.to(dtype);
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auto w_w = w.to(dtype);
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if (masks[0]) {
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grad_input.copy_(torch::mm(g_w, w_w).reshape_as(x));
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}
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if (masks[1]) {
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grad_weight.copy_(torch::mm(g_w.t(), x_c));
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}
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if (masks[2]) {
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grad_bias = g.sum(0).to(g.dtype());
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}
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return std::tuple<torch::Tensor, torch::Tensor, torch::Tensor>(
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grad_input, grad_weight, grad_bias);
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}
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PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
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m.def("fp8_mm_view", &fp8_mm_view, py::arg("a"), py::arg("b"),
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"FP8 GEMM returning raw col-major buffer (debug)");
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m.def("fp8_mm", &fp8_mm, py::arg("a"), py::arg("b"),
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"FP8 e4m3 GEMM: a[M,K] x b[N,K] -> fp32[M,N] (pre-scaled inputs)");
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"FP8 e4m3 GEMM: a[M,K] x b[N,K] -> bf16[M,N] (pre-scaled inputs)");
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m.def("fp8_linear_forward", &fp8_linear_forward,
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py::arg("x"), py::arg("w"), py::arg("bias"),
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"Fused FP8 linear forward: scale cast + cublasLt GEMM + unscale "
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"+ bias + transpose -> bf16, single call");
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m.def("fp8_linear_backward", &fp8_linear_backward,
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py::arg("g"), py::arg("x"), py::arg("w"), py::arg("masks"),
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"Fused linear backward: dX = g*sw @ W, dW = (g*sx)^T @ X, "
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"dB = sum(g), single call");
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}
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